公开(公告)号：US11354475B2

公开(公告)日：2022-06-07

申请号：US17089508

申请日：2020-11-04

Applicant: ANSYS, Inc.

Inventor： Joao Moreno Geada ,  Nicholas Lee Rethman ,  Ankur Gupta

IPC: G06F30/367 ,  G06F30/3312 ,  G06F30/36 ,  G06F119/06 ,  G06F119/12

Abstract: Systems and methods are provided for simulating an integrated circuit system. A file representative of an integrated circuit layout is received, the integrated circuit layout including a plurality of cells and characteristics of power supply and ground paths to each cell. A vulnerable cell of the integrated circuit layout based on a vulnerability characteristic of the vulnerable cell. A power analysis of a portion of the integrated circuit layout is performed to determine a plurality of power and ground levels within a timing window for each of a plurality of cells including the vulnerable cell. A timing analysis of the vulnerable cell is performed, where the timing analysis receives a single power level and single ground level for the vulnerable cell and determines a slack level for the vulnerable cell. An at risk path is identified based on the vulnerable cell slack level, and a dynamic power/ground simulation of one or more cells in the at risk path is performed.

公开(公告)号：US20240249055A1

公开(公告)日：2024-07-25

申请号：US18439639

申请日：2024-02-12

Applicant: ANSYS, INC.

Inventor： Joao Geada ,  Nicholas Lee Rethman

IPC: G06F30/367 ,  G06F30/3312 ,  G06F30/3315 ,  G06F30/38 ,  G06F119/12

CPC classification number: G06F30/367 ,  G06F30/3312 ,  G06F30/3315 ,  G06F30/38 ,  G06F2119/12

Abstract: Methods and systems for performing timing analysis during the design of a circuit are described. In one embodiment, a simulation system can generate an effective resistance value (or an impedance value based on the effective resistance value) for an instance and use the effective resistance value in a simulation to determine a minimum timing delay for the instance when only the instance switches during such simulations.

公开(公告)号：US11934760B1

公开(公告)日：2024-03-19

申请号：US17645882

申请日：2021-12-23

Applicant: ANSYS, INC.

Inventor： Joao Geada ,  Nicholas Lee Rethman

IPC: G06F30/30 ,  G06F30/3312 ,  G06F30/3315 ,  G06F30/367 ,  G06F30/38 ,  G06F119/12

CPC classification number: G06F30/367 ,  G06F30/3312 ,  G06F30/3315 ,  G06F30/38 ,  G06F2119/12

Abstract: Methods and systems for performing timing analysis during the design of a circuit are described. In one embodiment, a simulation system can generate an effective resistance value (or an impedance value based on the effective resistance value) for an instance and use the effective resistance value in a simulation to determine a minimum timing delay for the instance when only the instance switches during such simulations.

公开(公告)号：US20210056248A1

公开(公告)日：2021-02-25

申请号：US17089508

申请日：2020-11-04

Applicant: ANSYS, Inc.

Inventor： Joao Moreno Geada ,  Nicholas Lee Rethman ,  Ankur Gupta

IPC: G06F30/3312 ,  G06F30/36

Abstract: Systems and methods are provided for simulating an integrated circuit system. A file representative of an integrated circuit layout is received, the integrated circuit layout including a plurality of cells and characteristics of power supply and ground paths to each cell. A vulnerable cell of the integrated circuit layout based on a vulnerability characteristic of the vulnerable cell. A power analysis of a portion of the integrated circuit layout is performed to determine a plurality of power and ground levels within a timing window for each of a plurality of cells including the vulnerable cell. A timing analysis of the vulnerable cell is performed, where the timing analysis receives a single power level and single ground level for the vulnerable cell and determines a slack level for the vulnerable cell. An at risk path is identified based on the vulnerable cell slack level, and a dynamic power/ground simulation of one or more cells in the at risk path is performed.