公开(公告)号：US20190089337A1

公开(公告)日：2019-03-21

申请号：US15710526

申请日：2017-09-20

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Michael R Seningen ,  Ajay Bhatia

IPC: H03K3/037

Abstract: An electronic circuit is disclosed. A first flip-flop is coupled to receive a clock signal from clock gating circuit. The first flip-flop includes an input circuit having a data input, a master-slave latch, and an output circuit. Responsive to an edge of the clock signal, the master-slave latch may latch a logic value of a signal received on the data input. The output circuit is coupled to the master-slave latch, and provides a logic output signal corresponding to the logic value latched by the master-slave latch. The clock gating circuit may provide one or more inversions of the clock signal which it receives. The flip-flop provides no inversions of the clock signal.

公开(公告)号：US20140084234A1

公开(公告)日：2014-03-27

申请号：US13628743

申请日：2012-09-27

Applicant: APPLE INC.

Inventor： Michael R Seningen

IPC: H01L29/78 ,  H01L29/82 ,  H01L21/336 ,  H01L45/00

CPC classification number: H01L21/823864 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor device includes a channel strain altering material formed over or in the source and drain regions of the device. The channel strain altering material may be used to alter the strain in a channel region of the device after manufacturing of the device (e.g., after the device is formed or during operable use of the device). Changes in one or more of material properties of the channel strain altering material may be used to change the strain in the channel region. Changes in the material properties of the channel strain altering material may change a physical size or structure of the channel strain altering material. The channel strain altering material may include materials such as phase change materials or ferromagnetic materials.

Abstract translation: 半导体器件包括在器件的源极和漏极区域上方或其中形成的沟道应变改变材料。 通道应变改变材料可以用于在器件制造之后（例如在器件形成之后或在器件的可操作使用期间）改变器件的沟道区域中的应变。 可以使用通道应变改变材料的一种或多种材料性质的变化来改变通道区域中的应变。 通道应变改变材料的材料性质的改变可能改变通道应变改变材料的物理尺寸或结构。 通道应变改变材料可以包括诸如相变材料或铁磁材料的材料。

公开(公告)号：US10461747B2

公开(公告)日：2019-10-29

申请号：US15710406

申请日：2017-09-20

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Michael R Seningen ,  Ajay Bhatia

IPC: H03K19/00 ,  H03K5/134

Abstract: A clock gating circuit is disclosed. The clock gating circuit includes an input circuit configured to receive an enable signal and clock enable circuitry configured to receive an input clock signal. The clock gating circuit also includes a latch that captures and stores an enabled state of the enable signal when the enable signal is asserted. An output circuit is coupled to the latch, and provides an output signal corresponding to a state of the clock signal when the latch is storing the enabled state. The clock gating circuit is arranged such that, when the latch is not storing the enabled state, no dynamic power is consumed responsive to state changes of the input clock signal.

公开(公告)号：US20150207496A1

公开(公告)日：2015-07-23

申请号：US14160707

申请日：2014-01-22

Applicant: Apple Inc.

Inventor： Michael R Seningen

IPC: H03K3/356

CPC classification number: H03K3/356104

Abstract: Embodiments of a latch circuit are disclosed that may allow a reduction in storage time of data into the latch circuit. The latch circuit may include an input circuit, a first switch, a second switch, an input circuit, and an inverting amplifier. An input of the inverting amplifier may be coupled to a storage node, and an output of the inverting amplifier may be coupled to a feedback node. The input circuit may be configured to generate buffered and complement data dependent upon received data, and the switched may be configured to allow the generated buffered data to be transferred to the feedback node, and the complement data to be transferred to the storage node.

Abstract translation: 公开了锁存电路的实施例，其可以允许将数据的存储时间减少到锁存电路中。 锁存电路可以包括输入电路，第一开关，第二开关，输入电路和反相放大器。 反相放大器的输入可以耦合到存储节点，并且反相放大器的输出可以耦合到反馈节点。 输入电路可以被配置为根据接收到的数据产生缓冲和补码数据，并且切换可以被配置为允许生成的缓冲数据被传送到反馈节点，并且补码数据被传送到存储节点。