公开(公告)号：US20230384856A1

公开(公告)日：2023-11-30

申请号：US17664999

申请日：2022-05-25

Applicant: Apple Inc.

Inventor： Ping Zhou ,  Nikolai Schlegel ,  Navid Ehsan ,  Zhimin Chen ,  Gerard D. Jennings

IPC: G06F1/3296 ,  G06F13/16

CPC classification number: G06F1/3296 ,  G06F13/1668

Abstract: A processor can include various processing pipelines that perform different data processing operations, with different pipelines having dedicated logic and memory circuits. A power management circuit can determine when to supply power to various pipelines, including the logic and memory circuits of the various pipelines, depending on a current operating mode of the processor. When a memory circuit transitions to a lower power state such as a sleep state, data can be saved to a different memory circuit that is not transitioning to a lower power state, and when the memory circuit is powered up again, the data can be restored from the different memory circuit.

公开(公告)号：US20240241570A1

公开(公告)日：2024-07-18

申请号：US18412195

申请日：2024-01-12

Applicant: Apple Inc.

Inventor： Ping Zhou ,  Nikolai Schlegel ,  Navid Ehsan ,  Zhimin Chen ,  Gerard D. Jennings

IPC: G06F1/3296 ,  G06F13/16

CPC classification number: G06F1/3296 ,  G06F13/1668

Abstract: A processor can include various processing pipelines that perform different data processing operations, with different pipelines having dedicated logic and memory circuits. A power management circuit can determine when to supply power to various pipelines, including the logic and memory circuits of the various pipelines, depending on a current operating mode of the processor. When a memory circuit transitions to a lower power state such as a sleep state, data can be saved to a different memory circuit that is not transitioning to a lower power state, and when the memory circuit is powered up again, the data can be restored from the different memory circuit.

公开(公告)号：US11907043B2

公开(公告)日：2024-02-20

申请号：US17664999

申请日：2022-05-25

Applicant: Apple Inc.

Inventor： Ping Zhou ,  Nikolai Schlegel ,  Navid Ehsan ,  Zhimin Chen ,  Gerard D. Jennings

IPC: G06F1/3296 ,  G06F13/16

CPC classification number: G06F1/3296 ,  G06F13/1668

Abstract: A processor can include various processing pipelines that perform different data processing operations, with different pipelines having dedicated logic and memory circuits. A power management circuit can determine when to supply power to various pipelines, including the logic and memory circuits of the various pipelines, depending on a current operating mode of the processor. When a memory circuit transitions to a lower power state such as a sleep state, data can be saved to a different memory circuit that is not transitioning to a lower power state, and when the memory circuit is powered up again, the data can be restored from the different memory circuit.

公开(公告)号：US20240114424A1

公开(公告)日：2024-04-04

申请号：US18372039

申请日：2023-09-22

Applicant: Apple Inc.

Inventor： Parvathanathan Subrahmanya ,  Leilei Song ,  Mariam Motamed ,  Navid Ehsan ,  Sharad Sambhwani

IPC: H04W40/04

CPC classification number: H04W40/04

Abstract: Disclosed are methods, systems, and computer-readable medium to perform operations including obtaining first data regarding one or more applications running on a UE device, where the first data represents, for each of the one or more applications, an individual network usage characteristic of that application; determining, based on the first data, second data regarding the one or more applications, where the second data represents a composite network usage characteristic of the one or more applications; selecting, based on the second data, a first modem configuration from among a plurality of candidate modem configurations; and causing a modem of the UE device to operate according to the first modem configuration.

公开(公告)号：US20220346123A1

公开(公告)日：2022-10-27

申请号：US17655252

申请日：2022-03-17

Applicant: APPLE INC.

Inventor： Huaning Niu ,  Dawei Zhang ,  Farhan Aziz ,  Haitong Sun ,  Hong He ,  Navid Ehsan ,  Sigen Ye ,  Wei Zeng ,  Wei Zhang ,  Weidong Yang

IPC: H04W72/12 ,  H04L5/00 ,  H04W76/28

Abstract: A wireless communication system may adapt physical downlink control channel (PDCCH) monitoring behaviors using downlink control information (DCI). The change in monitoring behavior may be skipping or switching. The timeline for applying switching or skipping may be applied after a reference point and a processing time. In some embodiments, the processing time may be either based on UE processing, network processing, or a combination.