METHOD AND SYSTEM FOR WAFER LEVEL SINGULATION
    2.
    发明申请
    METHOD AND SYSTEM FOR WAFER LEVEL SINGULATION 审中-公开
    用于水平层叠的方法和系统

    公开(公告)号:US20140196850A1

    公开(公告)日:2014-07-17

    申请号:US14075603

    申请日:2013-11-08

    IPC分类号: H01L21/78 H01L21/02

    摘要: A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices. The method also includes forming a mask layer on the semiconductor substrate, exposing a predetermined portion of the mask layer to light, and processing the predetermined portion of the mask layer to form a predetermined mask pattern on the semiconductor substrate. The method further includes forming the plurality of semiconductor dies, each of the plurality of semiconductor dies being associated with the predetermined mask pattern and including one or more of the plurality of devices and separating the plurality of semiconductor dies from the carrier substrate.

    摘要翻译: 单片化多个半导体管芯的方法包括提供载体衬底并将半导体衬底接合到载体衬底。 半导体衬底包括多个器件。 该方法还包括在半导体衬底上形成掩模层,将掩模层的预定部分暴露于光,以及处理掩模层的预定部分以在半导体衬底上形成预定的掩模图案。 所述方法还包括形成所述多个半导体管芯,所述多个半导体管芯中的每一个与所述预定掩模图案相关联并且包括所述多个器件中的一个或多个并且将所述多个半导体管芯与所述载体衬底分离。