公开(公告)号：US20230275165A1

公开(公告)日：2023-08-31

申请号：US18133602

申请日：2023-04-12

申请人： Applied Materials, Inc.

发明人： Philip Hsin-hua Li ,  Seshadri Ramaswami

IPC分类号： H01L31/0392 ,  H01L31/0749 ,  H01L31/18

CPC分类号： H01L31/03928 ,  H01L31/0749 ,  H01L31/18

摘要： A method includes forming, on a substrate by performing physical vapor deposition in vacuum, an absorber layer including copper (Cu), indium (In), gallium (Ga) and selenium (Se), forming a stack including the substrate and an oxygen-annealed absorber layer by performing in-situ oxygen annealing of the absorber layer to improve quantum efficiency of the image sensor by passivating selenium vacancies due to dangling bonds, and forming a cap layer over the oxygen-annealed absorber layer by performing physical vapor deposition in vacuum. The cap layer includes at least one of: Ga2O3·Sn, ZnS, CdS, CdSe, ZnO, ZnSe, ZnIn2Se4, CuGaS2, In2S3, MgO, or Zn0.8Mg0.2O.

公开(公告)号：US11094573B2

公开(公告)日：2021-08-17

申请号：US16198569

申请日：2018-11-21

申请人： APPLIED MATERIALS, INC.

发明人： Jingyu Qiao ,  Qiwei Liang ,  Viachslav Babayan ,  Seshadri Ramaswami ,  Srinivas D. Nemani

IPC分类号： H01L21/683 ,  C23C16/56 ,  C23C16/40

摘要： Disclosed herein is an electrostatic chuck (ESC) carrier. The ESC carrier may comprise a carrier substrate having a first surface and a second surface opposite the first surface. A first through substrate opening and a second through substrate opening may pass through the carrier substrate from the first surface to the second surface. A first conductor is in the first through substrate opening, and a second conductor is in the second through substrate opening. The ESC carrier may further comprise a first electrode over the first surface of the carrier substrate and electrically coupled to the first conductor, and a second electrode over the first surface of the carrier substrate and electrically coupled to the second conductor. An oxide layer may be formed over the first electrode and the second electrode.

公开(公告)号：US10665494B2

公开(公告)日：2020-05-26

申请号：US15885120

申请日：2018-01-31

申请人： APPLIED MATERIALS, INC.

发明人： Niranjan Kumar ,  Seshadri Ramaswami ,  Shay Assaf ,  Amikam Sade ,  Andy Constant ,  Maureen Breiling

IPC分类号： H01L21/683 ,  H01L21/67 ,  H01L21/3065 ,  H01L21/687

摘要： Embodiments include a method for processing thin substrates. Embodiments may include electrostatically bonding a substrate to a first electrostatic carrier (ESC), with a backside of the substrate is facing away from the first ESC. Thereafter, the substrate may be thinned to form a thinned substrate. The thinned substrate may then be transferred to a second ESC with a front side of the thinned substrate facing away from the second ESC. Embodiments may include cleaning the front side surface of the thinned substrate and transferring the thinned substrate to a third ESC. In an embodiment, a backside of the thinned substrate is facing away from the third ESC. Embodiments may also include processing the backside surface of the thinned substrate, and transferring the thinned substrate to a tape frame.

公开(公告)号：US20180122679A1

公开(公告)日：2018-05-03

申请号：US15337973

申请日：2016-10-28

申请人： APPLIED MATERIALS, INC.

发明人： Shambhu N. Roy ,  Gautam Pisharody ,  Seshadri Ramaswami ,  Srinivas D. Nemani ,  Zhong Qiang Hua ,  Douglas A. Buchberger, JR. ,  Niranjan Kumar ,  Ellie Y. Yieh

IPC分类号： H01L21/683 ,  H01L21/67

CPC分类号： H01L21/67248 ,  H01L21/67103 ,  H01L21/67109 ,  H01L21/6831 ,  H01L21/6835 ,  H01L21/68785 ,  H01L2021/6006 ,  H01L2221/68304

摘要： A substrate carrier with contacts is described that is balanced for thermal stress. In one example workpiece carrier has a rigid substrate configured to support a workpiece to be carried for processing, a first dielectric layer over the substrate, an electrostatic conductive electrode over the first dielectric layer to electrostatically hold the workpiece to be carried, a second dielectric layer over the electrode to electrically isolate the workpiece from the electrode, and a third dielectric layer under the substrate to counter thermal stress applied to the substrate by the first and second dielectric layers.

公开(公告)号：US20210111297A1

公开(公告)日：2021-04-15

申请号：US16653750

申请日：2019-10-15

申请人： Applied Materials, Inc.

发明人： Philip Hsin-hua Li ,  Seshadri Ramaswami

IPC分类号： H01L31/109 ,  H01L31/18 ,  H01L31/032

摘要： Embodiments disclosed herein include photodiodes and methods of forming such photodiodes. In an embodiment, a method of creating a photodiode, comprises disposing an absorber layer over a first contact, wherein the absorber layer comprises a first conductivity type, and disposing a semiconductor layer over the absorber, wherein the semiconductor layer has a second conductivity type that is opposite from the first conductivity type. In an embodiment, the method further comprises disposing a hole blocking layer over the semiconductor layer, wherein the hole blocking layer is formed with a reactive sputtering process with a processing gas that comprises oxygen, and disposing a second contact over the hole blocking layer.

公开(公告)号：US20180144959A1

公开(公告)日：2018-05-24

申请号：US15360412

申请日：2016-11-23

申请人： APPLIED MATERIALS, INC.

发明人： Srinivas D. Nemani ,  Gautam Pisharody ,  Seshadri Ramaswami ,  Shambhu N. Roy ,  Niranjan Kumar

IPC分类号： H01L21/67 ,  H01L21/683 ,  G01R29/12

CPC分类号： H01L21/67288 ,  G01R29/12 ,  H01L21/67253 ,  H01L21/6831 ,  H01L21/6833 ,  H01L21/6838

摘要： An electrostatic chucking force tool is described that may be used on workpiece carriers for micromechanical and semiconductor processing. One example includes a workpiece fitting to hold a workpiece when gripped by an electrostatic chucking force by an electrostatic chuck, an arm coupled to the workpiece fitting to pull the workpiece through the workpiece fitting laterally across the chuck, and a force gauge coupled to the arm to measure an amount of force with which the workpiece fitting is pulled by the arm in order to move the workpiece.

公开(公告)号：US20140196850A1

公开(公告)日：2014-07-17

申请号：US14075603

申请日：2013-11-08

申请人： APPLIED MATERIALS, INC.

发明人： Klaus Schuegraf ,  Seshadri Ramaswami ,  Michael R. Rice ,  Mohsen S. Salek ,  Claes H. Bjorkman

IPC分类号： H01L21/78 ,  H01L21/02

CPC分类号： H01L21/78 ,  H01L21/02076 ,  H01L21/30 ,  H01L21/302 ,  H01L21/308 ,  H01L21/561 ,  H01L21/568 ,  H01L21/67017 ,  H01L21/67207 ,  H01L21/6836 ,  H01L23/544 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/00

摘要： A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices. The method also includes forming a mask layer on the semiconductor substrate, exposing a predetermined portion of the mask layer to light, and processing the predetermined portion of the mask layer to form a predetermined mask pattern on the semiconductor substrate. The method further includes forming the plurality of semiconductor dies, each of the plurality of semiconductor dies being associated with the predetermined mask pattern and including one or more of the plurality of devices and separating the plurality of semiconductor dies from the carrier substrate.

摘要翻译： 单片化多个半导体管芯的方法包括提供载体衬底并将半导体衬底接合到载体衬底。 半导体衬底包括多个器件。 该方法还包括在半导体衬底上形成掩模层，将掩模层的预定部分暴露于光，以及处理掩模层的预定部分以在半导体衬底上形成预定的掩模图案。 所述方法还包括形成所述多个半导体管芯，所述多个半导体管芯中的每一个与所述预定掩模图案相关联并且包括所述多个器件中的一个或多个并且将所述多个半导体管芯与所述载体衬底分离。

公开(公告)号：US09502294B2

公开(公告)日：2016-11-22

申请号：US14075603

申请日：2013-11-08

申请人： APPLIED MATERIALS, INC.

发明人： Klaus Schuegraf ,  Seshadri Ramaswami ,  Michael R. Rice ,  Mohsen S. Salek ,  Claes H. Bjorkman

IPC分类号： H01L21/30 ,  H01L21/302 ,  H01L21/00 ,  H01L21/78 ,  H01L21/46 ,  H01L21/683 ,  H01L23/544 ,  H01L21/67 ,  H01L21/308 ,  H01L21/56 ,  H01L21/02 ,  H01L23/00

CPC分类号： H01L21/78 ,  H01L21/02076 ,  H01L21/30 ,  H01L21/302 ,  H01L21/308 ,  H01L21/561 ,  H01L21/568 ,  H01L21/67017 ,  H01L21/67207 ,  H01L21/6836 ,  H01L23/544 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/00

摘要： A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices. The method also includes forming a mask layer on the semiconductor substrate, exposing a predetermined portion of the mask layer to light, and processing the predetermined portion of the mask layer to form a predetermined mask pattern on the semiconductor substrate. The method further includes forming the plurality of semiconductor dies, each of the plurality of semiconductor dies being associated with the predetermined mask pattern and including one or more of the plurality of devices and separating the plurality of semiconductor dies from the carrier substrate.

公开(公告)号：US20230326925A1

公开(公告)日：2023-10-12

申请号：US17715331

申请日：2022-04-07

申请人： Applied Materials, Inc.

发明人： Andrew Anthony Cockburn ,  Vanessa Pena ,  Daniel Philippe Cellier ,  John Tolle ,  Thomas Kirschenheiter ,  Wei Hong ,  Ellie Y. Yieh ,  Mehul Naik ,  Seshadri Ramaswami

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8238 ,  H01L29/66

CPC分类号： H01L27/0922 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/30604 ,  H01L21/823807 ,  H01L29/66742

摘要： Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers having a reduced selective removal rate. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in a range of from greater than 0% to 50% on an atomic basis; and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprise alternating layers of nanosheet channel layer that comprise silicon (Si) and nanosheet release layer that comprise doped silicon germanium (SiGe).

公开(公告)号：US11728449B2

公开(公告)日：2023-08-15

申请号：US16702107

申请日：2019-12-03

申请人： Applied Materials, Inc.

发明人： Philip Hsin-hua Li ,  Seshadri Ramaswami

IPC分类号： H01L31/0392 ,  H01L31/0749 ,  H01L31/18

CPC分类号： H01L31/03928 ,  H01L31/0749 ,  H01L31/18

摘要： Embodiments of the present disclosure relate to photovoltaic devices, CIGS containing films, and methods of manufacturing CIGS containing films and photovoltaic devices to improve quantum efficiency, reduce interface charges, electron losses, and electron re-combinations. The CIGS layers in the photovoltaic devices described herein may be deposited using physical vapor deposition, followed by in-situ oxygen annealing, and further followed by deposition of a cap layer over the CIGS layer without subjecting the CIGS layer to an air break.