公开(公告)号：US20150317158A1

公开(公告)日：2015-11-05

申请号：US14243949

申请日：2014-04-03

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Matthew Ashcraft ,  Christopher Nelson

IPC: G06F9/30

CPC classification number: G06F9/3004 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/3834

Abstract: A system and method are provided for simplifying load acquire and store release semantics that are used in reduced instruction set computing (RISC). Translating the semantics into micro-operations, or low-level instructions used to implement complex machine instructions, can avoid having to implement complicated new memory operations. Using one or more data memory barrier operations in conjunction with load and store operations can provide sufficient ordering as a data memory barrier ensures that prior instructions are performed and completed before subsequent instructions are executed.

Abstract translation: 提供了一种用于简化在简化指令集计算（RISC）中使用的负载获取和存储释放语义的系统和方法。 将语义转换为微操作或用于实现复杂机器指令的低级指令，可以避免执行复杂的新内存操作。 使用一个或多个数据存储器屏障操作结合加载和存储操作可以提供足够的顺序，因为数据存储器屏障确保在执行后续指令之前执行和完成先前的指令。

公开(公告)号：US20150160945A1

公开(公告)日：2015-06-11

申请号：US14100228

申请日：2013-12-09

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Matthew Ashcraft ,  Richard W. Thaik

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3842 ,  G06F9/30043 ,  G06F9/3834 ,  G06F9/3836

Abstract: Various aspects provide for detecting ordering violations in a memory system. A system includes a prediction component and an execution component. The prediction component predicts whether a load instruction in the system is associated with an instruction pipeline hazard. The execution component allocates the load instruction to a queue buffer in the system in response to a prediction that the load instruction is not associated with the instruction pipeline hazard.

Abstract translation: 各种方面提供用于检测存储器系统中的排序违规。 系统包括预测组件和执行组件。 预测组件预测系统中的加载指令是否与指令管道危险相关联。 执行组件响应于预测加载指令不与指令管道危险相关联地将加载指令分配给系统中的队列缓冲器。

公开(公告)号：US09880849B2

公开(公告)日：2018-01-30

申请号：US14100228

申请日：2013-12-09

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Matthew Ashcraft ,  Richard W. Thaik

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3842 ,  G06F9/30043 ,  G06F9/3834 ,  G06F9/3836

Abstract: Various aspects provide for detecting ordering violations in a memory system. A system includes a prediction component and an execution component. The prediction component predicts whether a load instruction in the system is associated with an instruction pipeline hazard. The execution component allocates the load instruction to a queue buffer in the system in response to a prediction that the load instruction is not associated with the instruction pipeline hazard.

公开(公告)号：US20150324203A1

公开(公告)日：2015-11-12

申请号：US14203896

申请日：2014-03-11

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Matthew Ashcraft ,  Richard W. Thaik

IPC: G06F9/38 ,  G06F12/08

CPC classification number: G06F12/0862 ,  G06F9/3806 ,  G06F9/3834 ,  G06F9/3838 ,  G06F12/0875

Abstract: Various aspects provide for facilitating prediction of instruction pipeline hazards in a processor system. A system comprises a fetch component and an execution component. The fetch component is configured for storing a hazard prediction associated with a group of memory access instructions in a buffer associated with branch prediction. The execution component is configured for executing a memory access instruction associated with the group of memory access instructions as a function of the hazard prediction entry. In an aspect, the hazard prediction entry is configured for predicting whether the group of memory access instructions is associated with an instruction pipeline hazard.

Abstract translation: 各方面提供了便于对处理器系统中的指令管线危险的预测。 系统包括获取组件和执行组件。 提取组件被配置用于存储与分支预测相关联的缓冲器中与一组存储器访问指令相关联的危险预测。 执行组件被配置为执行与该组存储器访问指令相关联的存储器访问指令作为危害预测条目的函数。 在一方面，危险预测条目被配置用于预测该组存储器访问指令是否与指令管道危险相关联。