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公开(公告)号：US09485039B1
公开(公告)日：2016-11-01
申请号：US14736874
申请日：2015-06-11
Applicant: APPLIED MICRO CIRCUITS CORPORATION
Inventor： Moshe Malkin , Tarun Gupta
Abstract: Techniques for calibrating interleaved analog-to-digital converter (ADC) arrays are presented. A transceiver comprises an ADC component comprising an array of interleaved sub-ADCs, and an auxiliary path associated with an auxiliary sub-ADC used to facilitate calibrating a sampling array by comparing the auxiliary path signal to signals of the sub-ADCs in the array. A calibration component employs a phase-interpolator and analog delay lines to adjust the auxiliary sub-ADC to enable the auxiliary sub-ADC to be lined up to any one of the sampling instants of the sampling array. The calibration component compares the auxiliary signal to sub-ADC signals, determines path differences between the sub-ADC paths based on the comparison results, and calibrates the sub-ADCs and sub-ADC paths to reduce the path differences to mitigate distortion in a digital stream produced from combining the digital substreams produced by the sub-ADCs in the array.
Abstract translation: 提出了校准交错模数转换器（ADC）阵列的技术。 收发器包括包括交错子ADC阵列的ADC组件，以及与辅助子ADC相关联的辅助路径，用于通过将辅助路径信号与阵列中的子ADC的信号进行比较来便于校准采样阵列。 校准组件采用相位内插器和模拟延迟线来调整辅助子ADC，使辅助子ADC能够排列到采样阵列的任何一个采样时刻。 校准组件将辅助信号与子ADC信号进行比较，根据比较结果确定子ADC路径之间的路径差异，并校准子ADC和子ADC路径以减少路径差异以减轻数字中的失真 通过组合由阵列中的子ADC产生的数字子流产生的流。
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公开(公告)号：US09025711B2
公开(公告)日：2015-05-05
申请号：US13965375
申请日：2013-08-13
Applicant: Applied Micro Circuits Corporation
Inventor： Moshe Malkin
CPC classification number: H03H17/0202 , H03H17/0213
Abstract: Techniques for fast filtering for a transceiver are presented. A multidimensional filter processor component (MDFPC) can perform configurations and adaptations of multiple digital filters of a transceiver. The MDFPC can treat multiple, separate filters of a transceiver as a single larger multidimensional filter, and jointly update the multiple filters in a single adaptation operation instead of performing multiple adaptation operations on multiple filters. To facilitate multidimensional filter adaptation, the MDFPC can manage respective cross-correlations associated with the inputs of the filters. The MDFPC can facilitate multidimensional filter adaptation by performing multidimensional filter adaptation in the frequency domain, wherein the adaptation can be performed in parallel for multiple frequency sub-channels. For each frequency sub-channel, the MDFPC can perform a filter adaptation, wherein respective filter adaptation matrices can be generated for respective frequency sub-channels to perform the update to facilitate managing different cross-correlations associated with different frequency sub-channels.
Abstract translation: 介绍了收发器快速滤波技术。 多维滤波处理器组件（MDFPC）可以执行收发器的多个数字滤波器的配置和调整。 MDFPC可以将收发器的多个单独的滤波器作为单个更大的多维滤波器来处理，并且在单个适配操作中联合更新多个滤波器，而不是在多个滤波器上执行多个适配操作。 为了便于多维滤波器适配，MDFPC可以管理与滤波器的输入相关联的相互交叉相关。 MDFPC可以通过在频域中执行多维滤波器适配来促进多维滤波器适应，其中可以针对多个频率子信道并行执行自适应。 对于每个频率子信道，MDFPC可以执行滤波器适配，其中可以为各个频率子信道生成各自的滤波器适配矩阵以执行更新以便于管理与不同频率子信道相关联的不同交叉相关。
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Patent Agency Ranking
公开(公告)号：US20150049847A1
公开(公告)日：2015-02-19
申请号：US13965375
申请日：2013-08-13
Applicant: APPLIED MICRO CIRCUITS CORPORATION
Inventor： Moshe Malkin
CPC classification number: H03H17/0202 , H03H17/0213
Abstract: Techniques for fast filtering for a transceiver are presented. A multidimensional filter processor component (MDFPC) can perform configurations and adaptations of multiple digital filters of a transceiver. The MDFPC can treat multiple, separate filters of a transceiver as a single larger multidimensional filter, and jointly update the multiple filters in a single adaptation operation instead of performing multiple adaptation operations on multiple filters. To facilitate multidimensional filter adaptation, the MDFPC can manage respective cross-correlations associated with the inputs of the filters. The MDFPC can facilitate multidimensional filter adaptation by performing multidimensional filter adaptation in the frequency domain, wherein the adaptation can be performed in parallel for multiple frequency sub-channels. For each frequency sub-channel, the MDFPC can perform a filter adaptation, wherein respective filter adaptation matrices can be generated for respective frequency sub-channels to perform the update to facilitate managing different cross-correlations associated with different frequency sub-channels.
Abstract translation: 介绍了收发器快速滤波技术。 多维滤波处理器组件（MDFPC）可以执行收发器的多个数字滤波器的配置和调整。 MDFPC可以将收发器的多个单独的滤波器作为单个更大的多维滤波器来处理，并且在单个适配操作中联合更新多个滤波器，而不是在多个滤波器上执行多个适配操作。 为了便于多维滤波器适配，MDFPC可以管理与滤波器的输入相关联的相互交叉相关。 MDFPC可以通过在频域中执行多维滤波器适配来促进多维滤波器适应，其中可以针对多个频率子信道并行执行自适应。 对于每个频率子信道，MDFPC可以执行滤波器适配，其中可以为各个频率子信道生成各自的滤波器适配矩阵以执行更新以便于管理与不同频率子信道相关联的不同交叉相关。
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公开(公告)号：US20160365970A1
公开(公告)日：2016-12-15
申请号：US15208769
申请日：2016-07-13
Applicant: APPLIED MICRO CIRCUITS CORPORATION
Inventor： Moshe Malkin , Tarun Gupta
CPC classification number: H04L7/0087 , H04B1/04 , H04L7/0025 , H04L7/0079 , H04L7/0091 , H04L43/087
Abstract: Various embodiments provide systems and methods for performing clock recovery on a received signal using a split loop architecture. A split loop timing recovery apparatus is provided comprising a first path configured for performing frequency offset tracking on a signal by adjusting a receiver clock frequency to match a remote transmitter frequency associated with the signal and a second path configured for tracking random jitter on the signal.
Abstract translation: 各种实施例提供了使用分割环路架构对接收到的信号执行时钟恢复的系统和方法。 提供了一种分路定时恢复装置，包括：第一路径，被配置为通过调整接收机时钟频率来匹配与该信号相关联的远程发射机频率和被配置用于跟踪该信号上的随机抖动的第二路径来对信号进行频率偏移跟踪。
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公开(公告)号：US09397822B1
公开(公告)日：2016-07-19
申请号：US14736754
申请日：2015-06-11
Applicant: APPLIED MICRO CIRCUITS CORPORATION
Inventor： Moshe Malkin , Tarun Gupta
CPC classification number: H04L7/0087 , H04B1/04 , H04L7/0025 , H04L7/0079 , H04L7/0091 , H04L43/087
Abstract: Various embodiments provide systems and methods for performing clock recovery on a received signal using a split loop architecture. A split loop timing recovery apparatus is provided comprising a first path configured for performing frequency offset tracking on a signal by adjusting a receiver clock frequency to match a remote transmitter frequency associated with the signal and a second path configured for tracking random jitter on the signal.
Abstract translation: 各种实施例提供了使用分割环路架构对接收到的信号执行时钟恢复的系统和方法。 提供了一种分路定时恢复装置，包括：第一路径，被配置为通过调整接收机时钟频率来匹配与该信号相关联的远程发射机频率和被配置用于跟踪该信号上的随机抖动的第二路径来对信号进行频率偏移跟踪。
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公开(公告)号：US09071262B1
公开(公告)日：2015-06-30
申请号：US14162899
申请日：2014-01-24
Applicant: APPLIED MICRO CIRCUITS CORPORATION
Inventor： Moshe Malkin
CPC classification number: H03M1/06 , H03M1/1038 , H03M1/1215 , H04B17/21 , H04L1/00
Abstract: Techniques for calibration of high-speed interleaved analog-to-digital converter (ADC) arrays are presented. A transceiver comprises an ADC component that comprises an array of sub-ADCs that can be interleaved to facilitate high-speed data communications. The ADC component processes signals received from a remote transmitter to facilitate recovering the received data. The transceiver can comprise a calibration component that determines transfer characteristics of the communication channel or medium between the transceiver and the remote transmitter, and the transfer characteristics of the remote transmitter to each of the sub-ADCs of the array, based on the recovered data. The calibration component calibrates sub-ADCs of the array to facilitate correcting sub-ADC path differences, based on the respective transfer characteristics, to facilitate mitigating distortions that would be caused by the path differences, wherein the calibration component can use channel estimation to determine the transfer functions of the sub-ADCs of the array.
Abstract translation: 提出了用于校准高速交错模数转换器（ADC）阵列的技术。 收发器包括一个ADC组件，它包括一个可以进行交错以便于高速数据通信的子ADC阵列。 ADC组件处理从远程发射机接收的信号，以便于恢复接收到的数据。 收发器可以包括校准组件，其基于恢复的数据确定收发器和远程发射器之间的通信信道或介质的传输特性以及远程发射机到阵列的每个子ADC的传输特性。 校准组件校准阵列的子ADC以便于基于相应的传输特性校正子ADC路径差异，以便于减轻由路径差引起的失真，其中校准组件可以使用信道估计来确定 阵列的子ADC的传递函数。
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公开(公告)号：US09716583B2
公开(公告)日：2017-07-25
申请号：US15208769
申请日：2016-07-13
Applicant: APPLIED MICRO CIRCUITS CORPORATION
Inventor： Moshe Malkin , Tarun Gupta
CPC classification number: H04L7/0087 , H04B1/04 , H04L7/0025 , H04L7/0079 , H04L7/0091 , H04L43/087
Abstract: Various embodiments provide systems and methods for performing clock recovery on a received signal using a split loop architecture. A split loop timing recovery apparatus is provided comprising a first path configured for performing frequency offset tracking on a signal by adjusting a receiver clock frequency to match a remote transmitter frequency associated with the signal and a second path configured for tracking random jitter on the signal.
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