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    High speed serializer using quadrature clocks
    1.
    发明授权
    High speed serializer using quadrature clocks 有权

    公开(公告)号：US10110334B2

    公开(公告)日：2018-10-23

    申请号：US15137187

    申请日：2016-04-25

    Applicant: APPLIED MICRO CIRCUITS CORPORATION

    Inventor： Vijay Gupta ,  Tarun Gupta

    IPC: H04J3/06 ,  H04L7/00 ,  H03M9/00 ,  H04J3/04

    Abstract: Techniques efficiently serialize multiple data streams using quadrature clocks. Serializer employs first, second, third, and fourth clock signals. Serializer receives multiple data streams via registers, with each of four paths comprising a register, buffer, and switch, with registers of first and fourth paths associated with third clock signal, and registers of second and third paths associated with first clock signal, and with switches of first and fourth paths associated with first clock signal, and switches of second and third paths associated with third clock signal. Switches of first and second paths transfer respective data bits to fifth switch via another buffer, wherein fifth switch is associated with a delayed second clock signal of a time delay component (TDC). Switches of third and fourth paths transfer respective data bits to sixth switch via another buffer, wherein sixth switch is associated with a delayed fourth clock signal of TDC.

    HIGH SPEED SERIALIZER USING QUADRATURE CLOCKS
    2.
    发明申请
    HIGH SPEED SERIALIZER USING QUADRATURE CLOCKS 审中-公开

    公开(公告)号：US20170310412A1

    公开(公告)日：2017-10-26

    申请号：US15137187

    申请日：2016-04-25

    Applicant: APPLIED MICRO CIRCUITS CORPORATION

    Inventor： Vijay Gupta ,  Tarun Gupta

    IPC: H04J3/06 ,  H04L7/00

    CPC classification number: H04J3/0691 ,  H03M9/00 ,  H04J3/047 ,  H04J3/0682 ,  H04J3/0685 ,  H04L7/0037

    Abstract: Techniques efficiently serialize multiple data streams using quadrature clocks. Serializer employs first, second, third, and fourth clock signals. Serializer receives multiple data streams via registers, with each of four paths comprising a register, buffer, and switch, with registers of first and fourth paths associated with third clock signal, and registers of second and third paths associated with first clock signal, and with switches of first and fourth paths associated with first clock signal, and switches of second and third paths associated with third clock signal. Switches of first and second paths transfer respective data bits to fifth switch via another buffer, wherein fifth switch is associated with a delayed second clock signal of a time delay component (TDC). Switches of third and fourth paths transfer respective data bits to sixth switch via another buffer, wherein sixth switch is associated with a delayed fourth clock signal of TDC.

    PROGRAMMABLE GAIN AMPLIFIER WITH CONTROLLED GAIN STEPS
    3.
    发明申请
    PROGRAMMABLE GAIN AMPLIFIER WITH CONTROLLED GAIN STEPS 有权
    具有控制增益步长的可编程增益放大器

    公开(公告)号：US20150326197A1

    公开(公告)日：2015-11-12

    申请号：US14162896

    申请日：2014-01-24

    Applicant: APPLIED MICRO CIRCUITS CORPORATION

    Inventor： Nanda Govind Jayaraman ,  Tarun Gupta

    IPC: H03G3/30

    CPC classification number: H03G3/30 ,  H03G1/0029

    Abstract: Provided is a programmable gain amplifier that includes controlled gain steps that dynamically control an output voltage in real-time. The programmable gain amplifier includes a first transistor and a second transistor that includes respective control ports, input ports, and output ports. The programmable gain amplifier also includes a resistor connected to the output ports of the transistors. Further, at least a third transistor is connected to the output ports, in parallel with the resistor. On applying a control voltage to the third transistor and applying an input voltage to the first control port, the second control port is selectively modified by the control voltage to produce a desired output at the first input port and the second input port

    Abstract translation: 提供了一种可编程增益放大器，其包括可实时动态地控制输出电压的受控增益步长。 可编程增益放大器包括第一晶体管和第二晶体管，其包括相应的控制端口，输入端口和输出端口。 可编程增益放大器还包括连接到晶体管的输出端口的电阻器。 此外，至少第三晶体管与电阻器并联连接到输出端口。 在对第三晶体管施加控制电压并向第一控制端口施加输入电压时，通过控制电压选择性地修改第二控制端口，以在第一输入端口和第二输入端口产生期望的输出

    Calibration and tracking of receiver
    4.
    发明授权
    Calibration and tracking of receiver 有权
    接收机的校准和跟踪

    公开(公告)号：US09485039B1

    公开(公告)日：2016-11-01

    申请号：US14736874

    申请日：2015-06-11

    Applicant: APPLIED MICRO CIRCUITS CORPORATION

    Inventor： Moshe Malkin ,  Tarun Gupta

    IPC: H03M1/10 ,  H04B17/21

    CPC classification number: H04B17/21 ,  H04B17/14

    Abstract: Techniques for calibrating interleaved analog-to-digital converter (ADC) arrays are presented. A transceiver comprises an ADC component comprising an array of interleaved sub-ADCs, and an auxiliary path associated with an auxiliary sub-ADC used to facilitate calibrating a sampling array by comparing the auxiliary path signal to signals of the sub-ADCs in the array. A calibration component employs a phase-interpolator and analog delay lines to adjust the auxiliary sub-ADC to enable the auxiliary sub-ADC to be lined up to any one of the sampling instants of the sampling array. The calibration component compares the auxiliary signal to sub-ADC signals, determines path differences between the sub-ADC paths based on the comparison results, and calibrates the sub-ADCs and sub-ADC paths to reduce the path differences to mitigate distortion in a digital stream produced from combining the digital substreams produced by the sub-ADCs in the array.

    Abstract translation: 提出了校准交错模数转换器（ADC）阵列的技术。 收发器包括包括交错子ADC阵列的ADC组件，以及与辅助子ADC相关联的辅助路径，用于通过将辅助路径信号与阵列中的子ADC的信号进行比较来便于校准采样阵列。 校准组件采用相位内插器和模拟延迟线来调整辅助子ADC，使辅助子ADC能够排列到采样阵列的任何一个采样时刻。 校准组件将辅助信号与子ADC信号进行比较，根据比较结果确定子ADC路径之间的路径差异，并校准子ADC和子ADC路径以减少路径差异以减轻数字中的失真 通过组合由阵列中的子ADC产生的数字子流产生的流。

    Programmable gain amplifier with controlled gain steps
    7.
    发明授权
    Programmable gain amplifier with controlled gain steps 有权
    具有受控增益步长的可编程增益放大器

    公开(公告)号：US09325287B2

    公开(公告)日：2016-04-26

    申请号：US14162896

    申请日：2014-01-24

    Applicant: APPLIED MICRO CIRCUITS CORPORATION

    Inventor： Nanda Govind Jayaraman ,  Tarun Gupta

    IPC: H03F3/45 ,  H03G3/30

    CPC classification number: H03G3/30 ,  H03G1/0029

    Abstract: Provided is a programmable gain amplifier that includes controlled gain steps that dynamically control an output voltage in real-time. The programmable gain amplifier includes a first transistor and a second transistor that includes respective control ports, input ports, and output ports. The programmable gain amplifier also includes a resistor connected to the output ports of the transistors. Further, at least a third transistor is connected to the output ports, in parallel with the resistor. On applying a control voltage to the third transistor and applying an input voltage to the first control port, the second control port is selectively modified by the control voltage to produce a desired output at the first input port and the second input port.

    Abstract translation: 提供了一种可编程增益放大器，其包括可实时动态地控制输出电压的受控增益步长。 可编程增益放大器包括第一晶体管和第二晶体管，其包括相应的控制端口，输入端口和输出端口。 可编程增益放大器还包括连接到晶体管的输出端口的电阻器。 此外，至少第三晶体管与电阻器并联连接到输出端口。 在对第三晶体管施加控制电压并向第一控制端口施加输入电压时，通过控制电压选择性地修改第二控制端口，以在第一输入端口和第二输入端口产生期望的输出。

    SPLIT LOOP TIMING RECOVERY
    8.
    发明申请
    SPLIT LOOP TIMING RECOVERY 有权
    分段循环时序恢复

    公开(公告)号：US20160365970A1

    公开(公告)日：2016-12-15

    申请号：US15208769

    申请日：2016-07-13

    Applicant: APPLIED MICRO CIRCUITS CORPORATION

    Inventor： Moshe Malkin ,  Tarun Gupta

    IPC: H04L7/00 ,  H04B1/04 ,  H04L12/26

    CPC classification number: H04L7/0087 ,  H04B1/04 ,  H04L7/0025 ,  H04L7/0079 ,  H04L7/0091 ,  H04L43/087

    Abstract: Various embodiments provide systems and methods for performing clock recovery on a received signal using a split loop architecture. A split loop timing recovery apparatus is provided comprising a first path configured for performing frequency offset tracking on a signal by adjusting a receiver clock frequency to match a remote transmitter frequency associated with the signal and a second path configured for tracking random jitter on the signal.

    Abstract translation: 各种实施例提供了使用分割环路架构对接收到的信号执行时钟恢复的系统和方法。 提供了一种分路定时恢复装置，包括：第一路径，被配置为通过调整接收机时钟频率来匹配与该信号相关联的远程发射机频率和被配置用于跟踪该信号上的随机抖动的第二路径来对信号进行频率偏移跟踪。

    Split loop timing recovery
    9.
    发明授权
    Split loop timing recovery 有权
    分路回路定时恢复

    公开(公告)号：US09397822B1

    公开(公告)日：2016-07-19

    申请号：US14736754

    申请日：2015-06-11

    Applicant: APPLIED MICRO CIRCUITS CORPORATION

    Inventor： Moshe Malkin ,  Tarun Gupta

    IPC: H03D3/24 ,  H04L7/00 ,  H04L12/26

    CPC classification number: H04L7/0087 ,  H04B1/04 ,  H04L7/0025 ,  H04L7/0079 ,  H04L7/0091 ,  H04L43/087

    Abstract: Various embodiments provide systems and methods for performing clock recovery on a received signal using a split loop architecture. A split loop timing recovery apparatus is provided comprising a first path configured for performing frequency offset tracking on a signal by adjusting a receiver clock frequency to match a remote transmitter frequency associated with the signal and a second path configured for tracking random jitter on the signal.

    Abstract translation: 各种实施例提供了使用分割环路架构对接收到的信号执行时钟恢复的系统和方法。 提供了一种分路定时恢复装置，包括：第一路径，被配置为通过调整接收机时钟频率来匹配与该信号相关联的远程发射机频率和被配置用于跟踪该信号上的随机抖动的第二路径来对信号进行频率偏移跟踪。

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