公开(公告)号：US20150248138A1

公开(公告)日：2015-09-03

申请号：US14193492

申请日：2014-02-28

Applicant: ARM LIMITED

Inventor： Brett Stanley FEERO ,  Michael Alan FILIPPO

IPC: G06F1/12 ,  G06F12/12

CPC classification number: G06F1/12 ,  G06F1/3225 ,  G06F1/3275 ,  G06F12/0835 ,  G06F2212/1028

Abstract: A storage circuit and method are provided for propagating data values across a clock boundary between a first clock domain and a second clock domain. A storage structure is provided with at least one entry, and write circuitry performs write operations in the first clock domain, where each write operation writes a data value into an entry of the storage structure identified by a write pointer. The write circuitry alters the write pointer between each write operation. Write pointer synchronisation circuitry then receives the write pointer and synchronises the write pointer indication to the second clock domain over a predetermined number of clock cycles of the second clock domain. Read circuitry performs read operations in the second clock domain, with each read operation reading a data value from an entry of the storage structure identified by a read pointer. However, for a read operation to be performed, it is necessary that the synchronised write pointer indication indicates that there is a data value written into the storage structure that is available to be read. Early update circuitry is configured, for a write operation, to alter the write pointer indication provided to the write pointer synchronisation circuitry a number of clock cycles of the first clock domain before the write operation is performed. That number of clock cycles is chosen dependent on the difference in clock speed between the first clock domain and the second clock domain, and the predetermined number of clock cycles of the second clock domain taken by the write pointer synchronisation circuitry to synchronise the write pointer indication to the second clock domain. Such an approach enables at least a part of the latency of the write pointer synchronisation circuitry to be hidden, thereby improving performance of the storage circuitry.

Abstract translation: 提供了一种用于在第一时钟域和第二时钟域之间的时钟边界上传播数据值的存储电路和方法。 存储结构设置有至少一个条目，并且写入电路在第一时钟域中执行写入操作，其中每个写入操作将数据值写入由写入指针识别的存储结构的条目中。 写入电路在每个写操作之间改变写指针。 写指针同步电路然后接收写指针，并在第二时钟域的预定数量的时钟周期上使写指针指示与第二时钟域同步。 读取电路在第二时钟域中执行读取操作，每次读取操作从读取指针识别的存储结构的条目读取数据值。 然而，对于要执行的读操作，同步的写指针指示必须指示存储有可读取的存储结构中的数据值。 早期更新电路被配置为用于写入操作，以在执行写入操作之前改变提供给写指针同步电路的写入指针指示第一时钟域的多个时钟周期。 根据第一时钟域和第二时钟域之间的时钟速度的差异以及由写指针同步电路取得的第二时钟域的预定数量的时钟周期来选择该数量的时钟周期，以使写指针指示 到第二个时钟域。 这种方法使得写指针同步电路的等待时间的至少一部分能够被隐藏，从而提高存储电路的性能。

公开(公告)号：US20150149809A1

公开(公告)日：2015-05-28

申请号：US14092417

申请日：2013-11-27

Applicant: ARM LIMITED

Inventor： Brett Stanley FEERO ,  Klas Magnus Bruce

IPC: G06F1/10 ,  G06F13/40

CPC classification number: G06F13/4059 ,  G06F2213/0038

Abstract: Asynchronous bridge circuitry provides data communication between source circuitry 4 in a source clock domain and destination circuitry 12 in a destinations clock domain. The asynchronous bridge circuitry includes first-in-first-out buffer 20, transmission path circuitry 14, which has an input end coupled to the source circuitry and an output end coupled to the first-in-first-out buffer. The transmission path circuitry has a transmission delay corresponding to a plurality of source clock cycles. Write pointer circuitry 22 located within the source clock domain at the output end 18 of the transmission path circuitry so as to generate a write pointer for the first-in-first-out buffer. Transmission control circuitry 26 located within the source clock domain at the input end 16 of the transmission path circuitry is configured to generate a transmission control signal which controls whether or not the source circuitry is permitted to send data. The transmission control circuitry includes tracking circuitry which stores one or more tracking values for tracking respective state variables of the first-in-first-out buffer and controlling whether or not the transmission control circuitry permits the sending of data from the source to the destination in dependence upon the generated control circuitry.

Abstract translation: 异步桥电路提供源时钟域中的源电路4与目的地时钟域中的目的地电路12之间的数据通信。 异步桥电路包括先进先出缓冲器20，传输路径电路14，其具有耦合到源电路的输入端和耦合到先进先出缓冲器的输出端。 传输路径电路具有对应于多个源时钟周期的传输延迟。 写指针电路22位于传输路径电路的输出端18处的源时钟域内，以便产生用于先进先出缓冲器的写指针。 位于传输路径电路的输入端16处的源时钟域内的传输控制电路26被配置为产生控制是否允许源电路发送数据的传输控制信号。 传输控制电路包括跟踪电路，其存储用于跟踪先进先出缓冲器的各个状态变量的一个或多个跟踪值，并且控制传输控制电路是否允许从源到目的地的数据发送 依赖于所产生的控制电路。