公开(公告)号：US20150121014A1

公开(公告)日：2015-04-30

申请号：US14061842

申请日：2013-10-24

Applicant: ARM LIMITED

Inventor： Ganesh Suryanarayan DASIKA ,  Rune HOLM

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F9/3455 ,  G06F9/383 ,  G06F9/3832 ,  G06F2212/6026

Abstract: A data processing device includes processing circuitry 20 for executing a first memory access instruction to a first address of a memory device 40 and a second memory access instruction to a second address of the memory device 40, the first address being different from the second address. The data processing device also includes prefetching circuitry 30 for prefetching data from the memory device 40 based on a stride length 70 and instruction analysis circuitry 50 for determining a difference between the first address and the second address. Stride refining circuitry 60 is also provided to refine the stride length based on factors of the stride length and factors of the difference calculated by the instruction analysis circuitry 50.

Abstract translation: 数据处理设备包括处理电路20，用于执行对存储器件40的第一地址的第一存储器访问指令和到存储器件40的第二地址的第二存储器访问指令，第一地址不同于第二地址。 数据处理装置还包括预取电路30，用于基于步幅长度70和指令分析电路50从存储器装置40预取数据，用于确定第一地址和第二地址之间的差异。 还提供跨步精炼电路60以基于步幅长度的因素和由指令分析电路50计算的差异的因素来细化步幅长度。

公开(公告)号：US20150121038A1

公开(公告)日：2015-04-30

申请号：US14061837

申请日：2013-10-24

Applicant: ARM LIMITED

Inventor： Ganesh Suryanarayan DASIKA ,  Rune HOLM ,  David Hennah MANSELL

IPC: G06F9/38

CPC classification number: G06F9/3455 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3887

Abstract: A single instruction multiple thread (SIMT) processor 2 includes execution circuitry 6, prefetch circuitry 12 and prefetch strategy selection circuitry 14. The prefetch strategy selection circuitry serves to detect one or more characteristics of a stream of program instructions that are being executed to identify whether or not a given data access instruction within a program will be executed a plurality of times. The prefetch strategy to use is selected from a plurality of selectable prefetch strategy in dependence upon the detection of such characteristics.

Abstract translation: 单指令多线程（SIMT）处理器2包括执行电路6，预取电路12和预取策略选择电路14.预取策略选择电路用于检测正在执行的程序指令流的一个或多个特性，以识别是否 或者不在程序内的给定的数据访问指令将被执行多次。 根据这种特征的检测，从多个可选择的预取策略中选择要使用的预取策略。

公开(公告)号：US20170364817A1

公开(公告)日：2017-12-21

申请号：US15182901

申请日：2016-06-15

Applicant: ARM LIMITED

Inventor： Yordan Petrov RAYKOV ,  Emre Özer ,  Ganesh Suryanarayan DASIKA

IPC: G06N7/00 ,  G06N99/00 ,  G01J5/00

CPC classification number: G06N7/005 ,  G01J5/0025 ,  G06N20/00 ,  G06Q10/00 ,  G06Q50/16

Abstract: A method for estimating a number of occupants in a region comprises receiving a time series of sensor values detected over a period of time by a motion sensor sensing motion in the region. A spread parameter indicative of the spread of the sensor values is determined. The number of occupants in the region is estimated based on the spread parameter.

公开(公告)号：US20150121019A1

公开(公告)日：2015-04-30

申请号：US14063161

申请日：2013-10-25

Applicant: Arm Limited

Inventor： Ganesh Suryanarayan DASIKA ,  Rune HOLM ,  Stephen John HILL

IPC: G06F12/06

CPC classification number: G06F12/0607 ,  G06F9/00 ,  G06F9/30109 ,  G06F9/3012 ,  G06F9/3887 ,  Y02D10/13

Abstract: A data processing device 100 comprises a plurality of storage circuits 130, 160, which store a plurality of data elements of the bits in an interleaved manner. Data processing device also comprises a consumer 110 with a number of lanes 120. The consumer is able to individually access each of the plurality of storage circuits 130, 160 in order to receive into the lanes 120 either a subset of the plurality of data elements or y bits of each of the plurality of data elements. The consumer 110 is also able to execute a common instruction of each of the plurality of lanes 120. The relationship of the bits is such that b is greater than y and is an integer multiple of y. Each of the plurality of storage circuits 130, 160 stores at most y bits of each of the data elements. Furthermore, each of the storage circuits 130, 160 stores at most y/b of the plurality of data elements. By carrying out the interleaving in this manner, the plurality of storage circuits 130, 160 comprise no more than b/y storage circuits.

Abstract translation: 数据处理设备100包括多个存储电路130,160，其以交错的方式存储位的多个数据元素。 数据处理设备还包括具有多个通道120的消费者110.消费者能够单独访问多个存储电路130,160中的每一个，以便接收多个数据元素的子集中的子集120或者， y比特的多个数据元素。 消费者110还能够执行多个通道120中的每一个的公共指令。比特的关系使得b大于y并且是y的整数倍。 多个存储电路130,160中的每一个存储每个数据元素的最多y位。 此外，存储电路130,160中的每一个存储多个数据元素中的至多y / b。 通过以这种方式进行交织，多个存储电路130,160包括不超过b / y存储电路。