公开(公告)号：US10678985B2

公开(公告)日：2020-06-09

申请号：US15252592

申请日：2016-08-31

Applicant: ARM LIMITED

Inventor： Saurabh Pijuskumar Sinha ,  Kyungwook Chang ,  Brian Tracy Cline ,  Ebbin Raney Southerland, Jr.

IPC: G06F30/34 ,  G06F30/392 ,  G06F30/394 ,  G06F30/3312

Abstract: A method for generating a design for a 3D integrated circuit (3DIC) comprises extracting at least one design characteristic from a first data representation of a design for a integrated circuit (2DIC) generated according to the design criteria required for the 3DIC. Components of the 3DIC are partitioned into groups (each representing one tier of the 3DIC) based on the extracted design characteristic. A second data representation of a 2DIC design is generated comprising multiple adjacent partitions each comprising the component groups for one tier of the 3DIC design together with inter-tier via ports representing locations of inter-tier vias. A placement for each partition is determined separately from a placement of corresponding components of the 2DIC represented by the original first data representation. This approach allows a 2DIC EDA tool to be used for designing a 3DIC.

公开(公告)号：US20170365600A1

公开(公告)日：2017-12-21

申请号：US15188544

申请日：2016-06-21

Applicant: ARM Limited

Inventor： Saurabh Pijuskumar Sinha ,  Robert Campbell Aitken ,  Brian Tracy Cline ,  Gregory Munson Yeric ,  Kyungwook Chang

IPC: H01L27/06 ,  H01L23/528 ,  H01L23/48 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L27/0688 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L24/14 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/13025 ,  H01L2224/73207

Abstract: Various implementations described herein may be directed to using inter-tier vias (IVs) in integrated circuits (ICs). In one implementation, a three-dimensional (3D) IC may include a plurality of tiers disposed on a substrate layer, where the tiers may include a first tier having a first active device layer electrically coupled to first interconnect layers, and may also include a second tier having a second active device layer electrically coupled to a second interconnect layer, where the first interconnect layers include an uppermost layer that is least proximate to the first active device layer. The 3D IC may further include IVs to electrically couple the second interconnect layer and the uppermost layer. The uppermost layer may be electrically coupled to a power source at peripheral locations of the first tier, thereby electrically coupling the power source to the first active device layer and to the second active device layer.

公开(公告)号：US09929149B2

公开(公告)日：2018-03-27

申请号：US15188544

申请日：2016-06-21

Applicant: ARM Limited

Inventor： Saurabh Pijuskumar Sinha ,  Robert Campbell Aitken ,  Brian Tracy Cline ,  Gregory Munson Yeric ,  Kyungwook Chang

IPC: H01L27/06 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L27/0688 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L24/14 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/13025 ,  H01L2224/73207

Abstract: Various implementations described herein may be directed to using inter-tier vias (IVs) in integrated circuits (ICs). In one implementation, a three-dimensional (3D) IC may include a plurality of tiers disposed on a substrate layer, where the tiers may include a first tier having a first active device layer electrically coupled to first interconnect layers, and may also include a second tier having a second active device layer electrically coupled to a second interconnect layer, where the first interconnect layers include an uppermost layer that is least proximate to the first active device layer. The 3D IC may further include IVs to electrically couple the second interconnect layer and the uppermost layer. The uppermost layer may be electrically coupled to a power source at peripheral locations of the first tier, thereby electrically coupling the power source to the first active device layer and to the second active device layer.

公开(公告)号：US11625522B2

公开(公告)日：2023-04-11

申请号：US16861286

申请日：2020-04-29

Applicant: ARM Limited

Inventor： Saurabh Pijuskumar Sinha ,  Kyungwook Chang ,  Brian Tracy Cline ,  Ebbin Raney Southerland, Jr.

IPC: G06F30/34 ,  G06F30/392 ,  G06F30/394 ,  G06F30/3312

Abstract: A method and apparatus for generating a design for a 3D integrated circuit (3DIC) comprises extracting at least one design characteristic from a first data representation of a design for a 2D integrated circuit (2DIC) generated according to the design criteria required for the 3DIC. Components of the 3DIC are partitioned into groups (each representing one tier of the 3DIC) based on the extracted design characteristic. A second data representation of a 2DIC design is generated comprising multiple adjacent partitions each comprising the component groups for one tier of the 3DIC design together with inter-tier via ports representing locations of inter-tier vias. A placement for each partition is determined separately from a placement of corresponding components of the 2DIC represented by the original first data representation. This approach allows a 2DIC EDA tool to be used for designing a 3DIC.