公开(公告)号：US20220075901A1

公开(公告)日：2022-03-10

申请号：US17012470

申请日：2020-09-04

Applicant: Arm Limited

Inventor： Carlo Dario Fanara ,  Frederic Jean Denis Arsanto ,  Luca Scalabrino

IPC: G06F21/75

Abstract: An electronic circuit includes a plurality of processing elements, a register bank, and a control circuit. The processing elements consume power by processing a plurality of operands to generate a plurality of result values. The register bank has a plurality of registers. The control circuit is configured to determine one or more unused processing elements among the processing elements by snooping one or more incoming operands and an instruction type, control routing of one or more random operands from the register bank to the unused processing elements, and control routing of a random result value generated by one of the unused processing elements into a trash register of the registers. The power consumed by the unused processing elements in the generation of the random result value and a write of the random result value into the trash register temporally blurs a total power consumed by the electronic circuit.

公开(公告)号：US10732980B2

公开(公告)日：2020-08-04

申请号：US16018492

申请日：2018-06-26

Applicant: ARM Limited

Inventor： Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Claire Aupetit

IPC: G06F9/34 ,  G06F12/08 ,  G06F9/38 ,  G06F9/30 ,  G06F12/0862

Abstract: An apparatus and method are provided for controlling use of a register cache. The apparatus has decode circuitry for decoding instructions retrieved from memory, execution circuitry to execute the decoded instructions in order to perform operations on data values, and a register file having a plurality of registers for storing the data values to be operated on by the execution circuitry. Further, a register cache is provided that comprises a plurality of entries, and is arranged to cache a subset of the data values. Each entry is arranged to cache a data value and an indication of the register associated with that cached data value. Prefetch circuitry is then used to prefetch data values from the register file into the register cache. Further, operand analysis circuitry derives source operand information for an instruction fetched from memory, at least prior to the decode circuitry completing decoding of that instruction. It then causes provision to the prefetch circuitry of at least one register identifier determined from the source operand information. The prefetch circuitry then utilises that at least one register identifier when determining which data values to prefetch into the register cache. Such an approach can significantly increase the hit rate within the register cache, hence improving performance.

公开(公告)号：US09311088B2

公开(公告)日：2016-04-12

申请号：US13927552

申请日：2013-06-26

Applicant: ARM Limited

Inventor： Frederic Claude Marie Piry ,  Louis-Marie Vincent Mouton ,  Luca Scalabrino ,  Richard Roy Grisenthwaite ,  David Hennah Mansell

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/455

CPC classification number: G06F9/30098 ,  G06F9/3012 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3861 ,  G06F9/45558

Abstract: An apparatus and method are provided for performing register renaming. Available register identifying circuitry is provided to identify which physical registers form a pool of physical registers available to be mapped by register renaming circuitry to an architectural register specified by an instruction to be executed. Configuration data whose value is modified during operation of the processing circuitry is stored such that, when the configuration data has a first value, the configuration data identifies at least one architectural register of the architectural register set which does not require mapping to a physical register by the register renaming circuitry. The register identifying circuitry is arranged to reference the modified data value, such that when the configuration data has the first value, the number of physical registers in the pool is increased due to the reduction in the number of architectural registers which require mapping to physical registers.

Abstract translation: 提供了一种用于执行寄存器重命名的装置和方法。 提供可用的寄存器识别电路以识别哪些物理寄存器形成可由寄存器重命名电路映射到由要执行的指令指定的架构寄存器的物理寄存器池。 存储其值在处理电路的操作期间被修改的配置数据，使得当配置数据具有第一值时，配置数据识别架构寄存器集合的至少一个体系结构寄存器，其不需要映射到物理寄存器 寄存器重命名电路。 寄存器识别电路被布置为引用修改的数据值，使得当配置数据具有第一值时，由于需要映射到物理寄存器的架构寄存器的数量的减少，池中的物理寄存器的数量增加 。

公开(公告)号：US10198267B2

公开(公告)日：2019-02-05

申请号：US15088368

申请日：2016-04-01

Applicant: ARM LIMITED

Inventor： Cedric Denis Robert Airaud ,  Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Thomas Gilles Tarridec

IPC: G06F9/38

Abstract: An apparatus has register rename circuitry to map architectural register specifiers specified by instructions to physical register specifiers identifying physical registers. A restoration table identifies at least one restoration mapping between an architectural register specifier and a previously mapped physical register specifier. Register reserving circuitry indicates one or more reserved register specifiers. In response to detecting that a speculative instruction corresponding to a restoration mapping has been committed when that instruction or an older instruction still could potentially read a register, the register reserving circuitry indicates the physical register specifier of that restoration mapping as reserved.

公开(公告)号：US11449642B2

公开(公告)日：2022-09-20

申请号：US17012470

申请日：2020-09-04

Applicant: Arm Limited

Inventor： Carlo Dario Fanara ,  Frederic Jean Denis Arsanto ,  Luca Scalabrino

IPC: G06F21/75

Abstract: An electronic circuit includes a plurality of processing elements, a register bank, and a control circuit. The processing elements consume power by processing a plurality of operands to generate a plurality of result values. The register bank has a plurality of registers. The control circuit is configured to determine one or more unused processing elements among the processing elements by snooping one or more incoming operands and an instruction type, control routing of one or more random operands from the register bank to the unused processing elements, and control routing of a random result value generated by one of the unused processing elements into a trash register of the registers. The power consumed by the unused processing elements in the generation of the random result value and a write of the random result value into the trash register temporally blurs a total power consumed by the electronic circuit.

公开(公告)号：US10789169B2

公开(公告)日：2020-09-29

申请号：US16018438

申请日：2018-06-26

Applicant: ARM Limited

Inventor： Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Claire Aupetit

IPC: G06F12/08 ,  G06F12/0862 ,  G06F9/38 ,  G06F9/30

Abstract: An apparatus and method are provided for controlling use of a register cache. The apparatus has execution circuitry for executing instructions to process data values, and a register file comprising a plurality of registers in which to store the data values for access by the execution circuitry. A register cache is also provided that has a plurality of entries and is arranged to cache a subset of the data values for access by the execution circuitry. Each entry is arranged to cache a data value and an indication of the register associated with that cached data value. Prefetch circuitry then performs prefetch operations to prefetch data values from the register file into the register cache. Timing indication storage is used to store, for each data value to be generated as a result of instructions being executed within the execution circuitry, a register identifier for that data value, and timing information indicating when that data value will be generated by the execution circuitry. Cache usage control circuitry is then responsive to receipt of a plurality of register identifiers associated with source data values for a pending instruction yet to be executed by the execution circuitry, to generate, with reference to the timing information in the timing indication storage, a timing control signal to control timing of at least one prefetch operation performed by the prefetch circuitry. Such an approach can lead to significant improvements in the efficiency of utilisation of the register cache.

公开(公告)号：US10545764B2

公开(公告)日：2020-01-28

申请号：US15082601

申请日：2016-03-28

Applicant: ARM LIMITED

Inventor： Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Thomas Gilles Tarridec ,  Cedric Denis Robert Airaud

IPC: G06F9/38

Abstract: A data processing apparatus comprises register rename circuitry for mapping architectural register specifiers specified by instructions to physical registers to be accessed in response to the instructions. Available register control circuitry controls which physical registers are available for mapping to an architectural register specifier by the register rename circuitry. For at least one group of two or more physical registers, the available register control circuitry controls availability of the registers based on a group tracking indication indicative of whether there is at least one pending access to any of the physical registers in the group.

公开(公告)号：US09361111B2

公开(公告)日：2016-06-07

申请号：US13737153

申请日：2013-01-09

Applicant: ARM LIMITED

Inventor： Luca Scalabrino ,  Melanie Emanuelle Lucie Teyssier ,  Cedric Denis Robert Airaud ,  Guillaume Schon

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3842 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3885

Abstract: First processing circuitry processes at least part of a stream of program instructions. The first processing circuitry has registers for storing data and register renaming circuitry for mapping architectural register specifiers to physical register specifiers. A renaming data store stores renaming entries for identifying a register mapping between the architectural and physical register specifiers. At least some renaming entries have a count value indicating a number of speculation points occurring between generation of a previous count value and generation of the count value. The speculation points may for example be branch operation or load/store operations.

Abstract translation: 第一处理电路处理程序指令流的至少一部分。 第一处理电路具有用于存储用于将体系结构寄存器说明符映射到物理寄存器说明符的数据和寄存器重命名电路的寄存器。 重命名数据存储存储用于识别架构和物理寄存器说明符之间的寄存器映射的重命名条目。 至少一些重命名条目具有指示在生成先前计数值和生成计数值之间发生的推测点数的计数值。 推测点可以例如是分支操作或加载/存储操作。

公开(公告)号：US09311087B2

公开(公告)日：2016-04-12

申请号：US13724046

申请日：2012-12-21

Applicant: ARM LIMITED

Inventor： Luca Scalabrino ,  Cédric Denis Robert Airaud ,  Guillaume Schon ,  Frederic Jean Denis Arsanto

IPC: G06F15/00 ,  G06F15/76 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30087 ,  G06F9/3804 ,  G06F9/3842 ,  G06F9/3865

Abstract: A data processing apparatus 2 supports speculative execution and the use of sticky bits. A different version of a sticky bit is associated with each segment of the speculative program flow. The segments of the program flow are separated by speculation nodes corresponding to program instructions which may be followed by a plurality of different alternative program instruction serving as the next program instruction. When a speculation node is resolved, then the segments separated by that speculation node are merged and the sticky bit values for those two segments are merged.

Abstract translation: 数据处理装置2支持推测执行和使用粘滞位。 粘性位的不同版本与推测程序流的每个段相关联。 节目流的片段由对应于节目指令的推测节点分开，节目指令可以跟随作为下一节目指令的多个不同的备选节目指令。 当一个猜测节点被解析时，由该推测节点分隔的段被合并，并且这两个段的粘滞位值被合并。

公开(公告)号：US11593111B2

公开(公告)日：2023-02-28

申请号：US16773059

申请日：2020-01-27

Applicant: Arm Limited

Inventor： Frederic Jean Denis Arsanto ,  Carlo Dario Fanara ,  Luca Scalabrino ,  Jean Sébastien Leroy

IPC: G06F9/30 ,  G06F9/38

Abstract: An apparatus and method are provided for inhibiting instruction manipulation. The apparatus has execution circuitry for performing data processing operations in response to a sequence of instructions from an instruction set, and decoder circuitry for decoding each instruction in the sequence in order to generate control signals for the execution circuitry. Each instruction comprises a plurality of instruction bits, and the decoder circuitry is arranged to perform a decode operation on each instruction to determine from the value of each instruction bit, and knowledge of the instruction set, the control signals to be issued to the execution circuitry in response to that instruction. An input path to the decoder circuitry comprises a set of wires over which the instruction bits of each instruction are provided. Scrambling circuitry is used to perform a scrambling function on each instruction using a secret scrambling key, such that the wire within the set of wires over which any given instruction bit is provided to the decoder circuitry is dependent on the secret scrambling key. The decode operation performed by the decoder circuitry is then adapted to incorporate a descrambling function using the secret scrambling key to reverse the effect of the scrambling function. As a result, independent of which wire any given instruction bit is provided on, the decode operation is arranged when decoding a given instruction to correctly interpret each instruction bit of that given instruction, based on knowledge of the instruction set, in order to determine from the value of each instruction bit the control signals to be issued to the execution circuitry in response to that given instruction.