公开(公告)号：US20220075901A1

公开(公告)日：2022-03-10

申请号：US17012470

申请日：2020-09-04

Applicant: Arm Limited

Inventor： Carlo Dario Fanara ,  Frederic Jean Denis Arsanto ,  Luca Scalabrino

IPC: G06F21/75

Abstract: An electronic circuit includes a plurality of processing elements, a register bank, and a control circuit. The processing elements consume power by processing a plurality of operands to generate a plurality of result values. The register bank has a plurality of registers. The control circuit is configured to determine one or more unused processing elements among the processing elements by snooping one or more incoming operands and an instruction type, control routing of one or more random operands from the register bank to the unused processing elements, and control routing of a random result value generated by one of the unused processing elements into a trash register of the registers. The power consumed by the unused processing elements in the generation of the random result value and a write of the random result value into the trash register temporally blurs a total power consumed by the electronic circuit.

公开(公告)号：US10732980B2

公开(公告)日：2020-08-04

申请号：US16018492

申请日：2018-06-26

Applicant: ARM Limited

Inventor： Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Claire Aupetit

IPC: G06F9/34 ,  G06F12/08 ,  G06F9/38 ,  G06F9/30 ,  G06F12/0862

Abstract: An apparatus and method are provided for controlling use of a register cache. The apparatus has decode circuitry for decoding instructions retrieved from memory, execution circuitry to execute the decoded instructions in order to perform operations on data values, and a register file having a plurality of registers for storing the data values to be operated on by the execution circuitry. Further, a register cache is provided that comprises a plurality of entries, and is arranged to cache a subset of the data values. Each entry is arranged to cache a data value and an indication of the register associated with that cached data value. Prefetch circuitry is then used to prefetch data values from the register file into the register cache. Further, operand analysis circuitry derives source operand information for an instruction fetched from memory, at least prior to the decode circuitry completing decoding of that instruction. It then causes provision to the prefetch circuitry of at least one register identifier determined from the source operand information. The prefetch circuitry then utilises that at least one register identifier when determining which data values to prefetch into the register cache. Such an approach can significantly increase the hit rate within the register cache, hence improving performance.

公开(公告)号：US10572262B2

公开(公告)日：2020-02-25

申请号：US15651158

申请日：2017-07-17

Applicant: ARM LIMITED

Inventor： Jocelyn Francois Orion Jaubert ,  Frederic Jean Denis Arsanto ,  Guillaume Schon ,  Carlo Dario Fanara

IPC: G06F9/38 ,  G06F9/30

Abstract: An apparatus comprises a set of registers and mapping circuitry to perform a mapping operation to map each of a set of register specifiers to a respective register from among the set of registers in dependence on a mapping function. The mapping function is dependent on a key value. In addition, the mapping for at least two register specifiers from among the set of register specifiers is dependent on the same key value.

公开(公告)号：US10902113B2

公开(公告)日：2021-01-26

申请号：US15793186

申请日：2017-10-25

Applicant: ARM Limited

Inventor： Guillaume Schon ,  Frederic Jean Denis Arsanto ,  Carlo Dario Fanara ,  Jocelyn François Orion Jaubert

IPC: H04L29/06 ,  G06F21/55 ,  G06F9/30 ,  G06F21/75 ,  G06F11/30

Abstract: Data processing circuitry comprises a set of two or more computational units to perform respective computational operations; an instruction decoder to decode successive data processing instructions and, for a given data processing instruction, to control one or more of the computational units to perform those computational operations required to execute the given data processing instruction; and control circuitry responsive to the given data processing instruction, to control one or more others of the computational units to perform further computational operations, other than the computational operations required to execute the given data processing instruction, during execution of the given data processing instruction.

公开(公告)号：US10198267B2

公开(公告)日：2019-02-05

申请号：US15088368

申请日：2016-04-01

Applicant: ARM LIMITED

Inventor： Cedric Denis Robert Airaud ,  Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Thomas Gilles Tarridec

IPC: G06F9/38

Abstract: An apparatus has register rename circuitry to map architectural register specifiers specified by instructions to physical register specifiers identifying physical registers. A restoration table identifies at least one restoration mapping between an architectural register specifier and a previously mapped physical register specifier. Register reserving circuitry indicates one or more reserved register specifiers. In response to detecting that a speculative instruction corresponding to a restoration mapping has been committed when that instruction or an older instruction still could potentially read a register, the register reserving circuitry indicates the physical register specifier of that restoration mapping as reserved.

公开(公告)号：US11593111B2

公开(公告)日：2023-02-28

申请号：US16773059

申请日：2020-01-27

Applicant: Arm Limited

Inventor： Frederic Jean Denis Arsanto ,  Carlo Dario Fanara ,  Luca Scalabrino ,  Jean Sébastien Leroy

IPC: G06F9/30 ,  G06F9/38

Abstract: An apparatus and method are provided for inhibiting instruction manipulation. The apparatus has execution circuitry for performing data processing operations in response to a sequence of instructions from an instruction set, and decoder circuitry for decoding each instruction in the sequence in order to generate control signals for the execution circuitry. Each instruction comprises a plurality of instruction bits, and the decoder circuitry is arranged to perform a decode operation on each instruction to determine from the value of each instruction bit, and knowledge of the instruction set, the control signals to be issued to the execution circuitry in response to that instruction. An input path to the decoder circuitry comprises a set of wires over which the instruction bits of each instruction are provided. Scrambling circuitry is used to perform a scrambling function on each instruction using a secret scrambling key, such that the wire within the set of wires over which any given instruction bit is provided to the decoder circuitry is dependent on the secret scrambling key. The decode operation performed by the decoder circuitry is then adapted to incorporate a descrambling function using the secret scrambling key to reverse the effect of the scrambling function. As a result, independent of which wire any given instruction bit is provided on, the decode operation is arranged when decoding a given instruction to correctly interpret each instruction bit of that given instruction, based on knowledge of the instruction set, in order to determine from the value of each instruction bit the control signals to be issued to the execution circuitry in response to that given instruction.

公开(公告)号：US20160350114A1

公开(公告)日：2016-12-01

申请号：US15088368

申请日：2016-04-01

Applicant: ARM LIMITED

Inventor： Cedric Denis Robert Airaud ,  Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Thomas Gilles Tarridec

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/384 ,  G06F9/3838 ,  G06F9/3859 ,  G06F9/3863

Abstract: An apparatus has register rename circuitry to map architectural register specifiers specified by instructions to physical register specifiers identifying physical registers. A restoration table identifies at least one restoration mapping between an architectural register specifier and a previously mapped physical register specifier. Register reserving circuitry indicates one or more reserved register specifiers. In response to detecting that a speculative instruction corresponding to a restoration mapping has been committed when that instruction or an older instruction still could potentially read a register, the register reserving circuitry indicates the physical register specifier of that restoration mapping as reserved.

Abstract translation: 一种装置具有寄存器重命名电路，用于将由指令指定的架构寄存器说明符映射到识别物理寄存器的物理寄存器说明符。 恢复表识别架构寄存器说明符和先前映射的物理寄存器说明符之间的至少一个恢复映射。 寄存器保留电路指示一个或多个保留寄存器说明符。 响应于检测到当该指令或较旧的指令仍然可能读取寄存器时已经提交了对应于恢复映射的推测指令时，寄存器保留电路将该恢复映射的物理寄存器说明符指示为保留。

公开(公告)号：US09424045B2

公开(公告)日：2016-08-23

申请号：US13752621

申请日：2013-01-29

Applicant: ARM LIMITED

Inventor： Cedric Denis Robert Airaud ,  Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Guillaume Schon ,  Frederic Claude Marie Piry ,  Albin Pierick Tonnerre

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/345 ,  G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/30014 ,  G06F9/30196

Abstract: An apparatus and method includes execution circuitry including a wide operand execution unit configured to allow up to N bits of operand data to be processed during execution of a single instruction. Decoder circuitry decodes and generates, for each instruction, at least one control data block identifying an operation to be performed by the execution circuitry and at least two re-combineable control data blocks for the instruction. Issue queue control circuitry then allocates a slot in the issue queue for each of the at least two data blocks and up to M bits of associated operand data, and marks those allocated slots to identify that they contain re-combineable control data blocks. The issue queue control circuitry issues the combined block to said wide operand execution unit along with the operand data contained in each of the allocated slots for said at least two control data blocks.

Abstract translation: 一种装置和方法包括执行电路，其包括宽操作数执行单元，其被配置为允许在单个指令的执行期间处理最多N位的操作数数据。 解码器电路针对每个指令对至少一个控制数据块进行解码并生成至少一个控制数据块，该控制数据块标识由执行电路执行的操作和用于该指令的至少两个可重新组合的控制数据块。 发出队列控制电路然后为发送队列中的每个至少两个数据块和相关操作数数据的高达M位分配一个时隙，并标记这些分配的时隙以标识它们包含可重新组合的控制数据块。 所述问题队列控制电路与包含在所述至少两个控制数据块的所分配的时隙中的操作数数据一起向所述宽操作数执行单元发出组合块。

公开(公告)号：US09286069B2

公开(公告)日：2016-03-15

申请号：US13723974

申请日：2012-12-21

Applicant: ARM LIMITED

Inventor： Cédric Denis Robert Airaud ,  Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Guillaume Schon

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/30014 ,  G06F9/30141 ,  G06F9/3857

Abstract: Within a processing pipeline 14, issue control circuitry 12 serves to arbitrate write port availability when floating point multiplication instructions are issued into a floating point pipeline 14. If not operating in a flush-to-zero mode, then depending upon the output operands generated denormal handling may or may not be required. A pessimistic assumption is made upon issue that denormal handling will be required and accordingly the write port reserved is a first predetermined number of processing cycles after the start cycle to take account of use of the denormal handling pipeline stage 20. Partway along the processing pipeline 14, state becomes available which indicates whether or not denormal handling is actually required. If denormal handling is not required and a write port is available one processing cycle earlier, then bypass circuitry 22 serves to bypass the denormal handling pipeline stage 20 such that the output operand will be written to the register bank 16 one processing cycle earlier. Write port usage is tracked by a write port usage scoreboard 26 which is both read and updated by the bypass circuitry 22 when re-arbitrating write port availability partway through a floating point multiplication instruction passing along the pipeline 14.

Abstract translation: 在处理流水线14内，发布控制电路12用于在将浮点乘法指令发布到浮点流水线14时仲裁写端口的可用性。如果不是以冲零模式运行，则根据产生的非正规输出操作数 处理可能或可能不需要。 在需要进行异常处理的问题上做出悲观的假设，因此，保留的写入端口是在开始周期之后的第一预定数量的处理周期，以考虑使用异常处理流水线级20。沿着处理流水线14 ，状态变为可用，其指示是否实际需要异常处理。 如果不需要异常处理并且写入端口可用于处理周期之前，则旁路电路22用于绕过异常处理流水线级20，使得输出操作数将被更早地写入一个处理周期的寄存器组16。 写端口使用记录板26由写入端口使用记分板26跟踪，当通过沿管线14传送的浮点乘法指令重新协商写入端口可用性时，旁路电路22读取和更新。

公开(公告)号：US10445500B2

公开(公告)日：2019-10-15

申请号：US15635614

申请日：2017-06-28

Applicant: ARM Limited

Inventor： Guillaume Schon ,  Frederic Jean Denis Arsanto ,  Jocelyn François Orion Jaubert ,  Carlo Dario Fanara

IPC: G06F21/56 ,  G06F3/06 ,  G06F21/62 ,  G06F21/78 ,  G06F21/57

Abstract: An apparatus has a number of data holding elements for holding data values which are reset to a reset value in response to a transition of a signal at a reset signal input of the data holding element from a first value to a second value. A reset tree is provided to distribute a reset signal received at root node of the reset tree to the reset signal inputs of the data holding elements. At least one reset attack detection element is provided, with its reset signal input coupled to a given node of the reset tree, to assert an error signal when its reset signal input transitions from the first value to a second value. Reset error clearing circuitry triggers clearing of the error signal, when the reset signal at the root node of the reset tree transitions from the second value to the first value.