公开(公告)号：US09513925B2

公开(公告)日：2016-12-06

申请号：US14031281

申请日：2013-09-19

Applicant: ARM LIMITED

Inventor： Nicolas Chaussade ,  Florent Begon ,  Melanie Emanuelle Lucie Teyssier ,  Remi Teyssier ,  Jocelyn Francois Orion Jaubert

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3861 ,  G06F9/30145 ,  G06F9/3842 ,  G06F9/3863

Abstract: A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions. Checkpoint circuitry is configured to identify an instance of a predetermined type of instruction in the sequence of program instructions and to store checkpoint information associated with that instance. The checkpoint information identifies a state of the data processing apparatus prior to execution of that instance of the predetermined type of instruction, wherein the predetermined type of instruction has an expected long completion latency. If the execution circuitry does not complete execution of that instance of the predetermined type of instruction due to occurrence of a predetermined event, the data processing apparatus is arranged to reinstate the state of the data processing apparatus with reference to the checkpoint information, such that the execution circuitry is then configured to recommence execution of the sequence of program instructions at that instance of the predetermined type of instruction.

Abstract translation: 提供数据处理装置和数据处理方法。 该数据处理装置包括被配置为执行程序指令序列的执行电路。 检查点电路被配置为识别程序指令序列中的预定类型的指令的实例，并且存储与该实例相关联的检查点信息。 检查点信息在执行预定类型的指令的该实例之前识别数据处理装置的状态，其中预定类型的指令具有期望的长完成延迟。 如果执行电路由于发生预定事件而没有完成预定类型的指令的实例的执行，则数据处理装置被配置为参照检查点信息恢复数据处理装置的状态，使得 然后，执行电路被配置为在预定类型的指令的那个情况下重新开始执行程序指令的序列。

公开(公告)号：US09170819B2

公开(公告)日：2015-10-27

申请号：US13737137

申请日：2013-01-09

Applicant: ARM LIMITED

Inventor： Nicolas Chaussade ,  Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Cedric Denis Robert Airaud

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3867 ,  G06F9/30072 ,  G06F9/3826

Abstract: A data processing apparatus comprises first and second processing circuitry. A conditional instruction executed by the second processing circuitry may have an outcome which is dependent on one of a plurality of sets of condition information maintained by the first processing circuitry. A first forwarding path can forward the sets of condition information from the first processing circuitry to a predetermined pipeline stage of a processing pipeline of the second processing circuitry. A request path can transmit a request signal from the second processing circuitry to the first processing circuitry, the request signal indicating a requested set of condition information which was not yet valid when a conditional instruction was at the predetermined pipeline stage. A second forwarding path may forward the requested set of condition information to a subsequent pipeline stage when the information becomes valid.

Abstract translation: 数据处理装置包括第一和第二处理电路。 由第二处理电路执行的条件指令可以具有取决于由第一处理电路维护的多组条件信息之一的结果。 第一转发路径可将来自第一处理电路的条件信息集合转发到第二处理电路的处理流水线的预定流水线级。 请求路径可以将来自第二处理电路的请求信号发送到第一处理电路，该请求信号指示当条件指令处于预定流水线阶段时尚未有效的请求的条件信息集合。 当信息变得有效时，第二转发路径可以将所请求的条件信息集合转发到后续流水线级。