公开(公告)号：US20180123571A1

公开(公告)日：2018-05-03

申请号：US15336721

申请日：2016-10-27

Applicant: ARM Limited ,  University of Southampton

Inventor： Anand Savanth ,  James Edward Myers ,  Yunpeng Cai ,  Alexander Stewart Weddell ,  Tom Kazmierski

IPC: H03K3/3562 ,  H03K19/20

CPC classification number: H03K3/35625 ,  H03K19/20

Abstract: A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.

公开(公告)号：US20180150120A1

公开(公告)日：2018-05-31

申请号：US15361405

申请日：2016-11-26

Applicant: ARM Limited

Inventor： Parameshwarappa Anand Kumar Savanth ,  Bal S. Sandhu ,  James Edward Myers ,  Alexander Stewart Weddell ,  David Walter Flynn

IPC: G06F1/28 ,  G01R19/165

CPC classification number: G06F1/28 ,  G01R19/16576

Abstract: Broadly speaking, embodiments of the present techniques provide a voltage monitoring circuit for low power minimum-energy sensor nodes. The circuit comprises sensing circuitry to sense a monitored signal having a plurality of operating signal states; a first comparator having a first input for receiving an upper threshold signal; and a second comparator having a first input for receiving a lower threshold signal, the upper and lower threshold signals defining a range which includes at least one signal state of the plurality of operating states of the monitored signal, wherein the first and second comparators have a bias input for receiving a bias configuration setting, the bias configuration setting being selectable according to an operating signal state of the monitored signal.

公开(公告)号：US09985613B2

公开(公告)日：2018-05-29

申请号：US15336721

申请日：2016-10-27

Applicant: ARM Limited ,  University of Southampton

Inventor： Anand Savanth ,  James Edward Myers ,  Yunpeng Cai ,  Alexander Stewart Weddell ,  Tom Kazmierski

IPC: H03K3/356 ,  H03K3/3562 ,  H03K19/20

CPC classification number: H03K3/35625 ,  H03K19/20

Abstract: A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.

公开(公告)号：US10664031B2

公开(公告)日：2020-05-26

申请号：US15361405

申请日：2016-11-26

Applicant: ARM Limited

Inventor： Parameshwarappa Anand Kumar Savanth ,  Bal S. Sandhu ,  James Edward Myers ,  Alexander Stewart Weddell ,  David Walter Flynn

IPC: G06F1/00 ,  G06F1/28 ,  G01R19/165

Abstract: Broadly speaking, embodiments of the present techniques provide a voltage monitoring circuit for low power minimum-energy sensor nodes. The circuit comprises sensing circuitry to sense a monitored signal having a plurality of operating signal states; a first comparator having a first input for receiving an upper threshold signal; and a second comparator having a first input for receiving a lower threshold signal, the upper and lower threshold signals defining a range which includes at least one signal state of the plurality of operating states of the monitored signal, wherein the first and second comparators have a bias input for receiving a bias configuration setting, the bias configuration setting being selectable according to an operating signal state of the monitored signal.

公开(公告)号：US20180278244A1

公开(公告)日：2018-09-27

申请号：US15990538

申请日：2018-05-25

Applicant: ARM Limited ,  University of Southampton

Inventor： Anand Savanth ,  James Edward Myers ,  Yunpeng Cai ,  Alexander Stewart Weddell ,  Tom Kazmierski

IPC: H03K3/3562 ,  H03K19/20

CPC classification number: H03K3/35625 ,  H03K19/20

Abstract: A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.