Power clamp with correlated electron material device

    公开(公告)号:US10734805B2

    公开(公告)日:2020-08-04

    申请号:US15381393

    申请日:2016-12-16

    Applicant: ARM Limited

    Abstract: A circuit is provided for limiting an applied voltage applied between a power line and an electrical ground. The circuit includes a transistive element connected between the power line and the electrical ground to provide a channel, where current flow through the channel is controlled by a control voltage provided to a control terminal of the transistive element. A first Correlated Electron Material (CEM) device having an impedance state is coupled between the power line and a first node, and a sensing circuit coupled between the first node and the control terminal of the transistive element. The sensing circuit is configured to detect a voltage drop across the CEM device and to provide the control voltage. The channel of the transistive element is opened when the detected voltage drop across the CEM device exceeds a threshold. The CEM device may contain a transition metal oxide (TMO), for example.

    Apparatus and method for masking power consumption of a processor

    公开(公告)号:US11188682B2

    公开(公告)日:2021-11-30

    申请号:US16378256

    申请日:2019-04-08

    Applicant: ARM Limited

    Abstract: An apparatus for masking power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises power-complementing circuitry configured to provide a second power consumption to directly power-complementing the power consumption associated with the one or more operations of the logic circuitry. The second power consumption complements the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The power-complementing circuitry and the header circuitry are each coupled to the logic circuitry at the common node.

    Controlling voltage generation and voltage comparison

    公开(公告)号:US09496785B2

    公开(公告)日:2016-11-15

    申请号:US14922783

    申请日:2015-10-26

    Applicant: ARM Limited

    CPC classification number: H02M3/157 G01R19/0084 H02M3/07 Y02B70/16

    Abstract: An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage.

    Power-On-Reset Detector
    6.
    发明申请
    Power-On-Reset Detector 有权
    上电复位检测器

    公开(公告)号:US20160308514A1

    公开(公告)日:2016-10-20

    申请号:US14687526

    申请日:2015-04-15

    Applicant: ARM Limited

    CPC classification number: H03K17/223 H03K3/3565

    Abstract: Various implementations described herein are directed to an integrated circuit for power-on-reset detection. The integrated circuit may include a first stage configured to receive an input voltage signal and provide a triggering signal during ramp of the input voltage signal. The integrated circuit may include a second stage configured to receive the triggering signal from the first stage and provide an output voltage signal during ramp of the input voltage signal via gate leakage through at least one transistor.

    Abstract translation: 本文描述的各种实现涉及用于上电复位检测的集成电路。 集成电路可以包括被配置为接收输入电压信号并且在输入电压信号的斜坡期间提供触发信号的第一级。 集成电路可以包括第二级,其被配置为从第一级接收触发信号,并且在通过至少一个晶体管的栅极泄漏的输入电压信号的斜坡期间提供输出电压信号。

    Monitoring circuit and method
    7.
    发明授权

    公开(公告)号:US10664031B2

    公开(公告)日:2020-05-26

    申请号:US15361405

    申请日:2016-11-26

    Applicant: ARM Limited

    Abstract: Broadly speaking, embodiments of the present techniques provide a voltage monitoring circuit for low power minimum-energy sensor nodes. The circuit comprises sensing circuitry to sense a monitored signal having a plurality of operating signal states; a first comparator having a first input for receiving an upper threshold signal; and a second comparator having a first input for receiving a lower threshold signal, the upper and lower threshold signals defining a range which includes at least one signal state of the plurality of operating states of the monitored signal, wherein the first and second comparators have a bias input for receiving a bias configuration setting, the bias configuration setting being selectable according to an operating signal state of the monitored signal.

    CMOS process skew sensor
    8.
    发明授权

    公开(公告)号:US10571516B2

    公开(公告)日:2020-02-25

    申请号:US15691722

    申请日:2017-08-30

    Applicant: ARM Limited

    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include converter circuitry that operates to provide a drive current. The integrated circuit may include process detector circuitry having multiple drive strength devices that are driven by the drive current from the converter circuitry. The multiple drive strength devices may provide multiple drive strength signals based on the drive current. The integrated circuit may include comparator circuitry having a comparator that receives the multiple drive strength signals from the multiple drive strength devices, detects a voltage difference between the multiple drive strength signals, and provides an output signal based on the detected voltage difference.

    Apparatus and Method for Masking Power Consumption of a Processor

    公开(公告)号:US20190236315A1

    公开(公告)日:2019-08-01

    申请号:US16378256

    申请日:2019-04-08

    Applicant: ARM Limited

    CPC classification number: G06F21/755 G06F1/28

    Abstract: An apparatus for masking power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises power-complementing circuitry configured to provide a second power consumption to directly power-complementing the power consumption associated with the one or more operations of the logic circuitry. The second power consumption complements the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The power-complementing circuitry and the header circuitry are each coupled to the logic circuitry at the common node.

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