公开(公告)号：US09213650B2

公开(公告)日：2015-12-15

申请号：US14560464

申请日：2014-12-04

Applicant: ARM Limited

Inventor： Erik Persson ,  Ola Hugosson ,  Andreas Bjorklund

IPC: G06F12/10 ,  G06F12/12

CPC classification number: G06F12/1018 ,  G06F12/1027 ,  G06F12/122

Abstract: A data processing apparatus is provided comprising a plurality of master devices configured to issue memory access requests including virtual addresses. A memory management unit is configured to receive memory access requests and to translate a virtual address included in a memory access request from a requesting master device into a physical address indicating a storage location in memory. The memory management unit has an internal storage unit having a plurality of entries wherein indications of corresponding virtual address portions and physical address portions are stored. The memory management unit is configured to select an entry of the internal storage unit in dependence on the virtual address and an identifier of the requesting master device. Conflict between the master devices in their usage of the internal storage unit is thus avoided.

Abstract translation: 提供了一种数据处理装置，包括被配置为发布包括虚拟地址的存储器访问请求的多个主设备。 存储器管理单元被配置为接收存储器访问请求并将包括在存储器访问请求中的虚拟地址从请求主设备转换成指示存储器中的存储位置的物理地址。 存储器管理单元具有内部存储单元，其具有多个条目，其中存储对应的虚拟地址部分和物理地址部分的指示。 存储器管理单元被配置为根据虚拟地址和请求主设备的标识符来选择内部存储单元的条目。 因此避免了主设备在使用内部存储单元时的冲突。