公开(公告)号：US10102160B2

公开(公告)日：2018-10-16

申请号：US14581290

申请日：2014-12-23

Applicant: ARM Limited

Inventor： Michael Kennedy ,  Simon John Craske ,  Andrew Turner ,  Richard Anthony Lane

IPC: G06F13/32 ,  G06F13/16

Abstract: A data processing system includes an interrupt controller having a priority level arbitrator and trigger circuitry. The priority level arbitrator and the trigger circuitry operate in parallel to process interrupt signals received by an interrupt signal receiver. The trigger circuitry generates a trigger signal initiating interrupt processing before the priority level arbitrator has completed its arbitration determination at an arbitration-completed time. If the interrupt processing triggered by the trigger signal was inappropriate, then is terminated once the result of the arbitration is known after the arbitration-completed time.