公开(公告)号：US20210149833A1

公开(公告)日：2021-05-20

申请号：US16685082

申请日：2019-11-15

Applicant: Arm Limited

Inventor： Tushar P. RINGE ,  Jamshed JALAL ,  Gurunath RAMAGIRI ,  Ashok Kumar TUMMALA ,  Mark David WERKHEISER

IPC: G06F13/40 ,  G06F9/46

Abstract: An apparatus and method are provided for handling ordered transactions. The apparatus has a plurality of completer elements to process transactions, a requester element to issue a sequence of ordered transactions, and an interconnect providing, for each completer element, a communication channel between that completer element and the requester element for transfer of signals between that completer element and the requester element in either direction. A given completer element that is processing a given transaction in the sequence is arranged to issue a response signal to the requester element over its associated communication channel that comprises an ordered channel indication to identify whether the associated communication channel has an ordered channel property. The ordered channel property guarantees that processing of transactions issued by the requester element over the associated communication channel in a given order will be completed by the given completer element in the same given order. The requester element is then responsive to the ordered channel indication to control timing of issuance from the requester element of at least one signal relating to one or more transactions after the given transaction in the sequence. By such an approach, the ordering flow adopted for ordered transactions can be varied by the requester element in dependence on the presence or absence of an ordered channel, whilst enabling interconnect-agnostic requester element designs to be utilised.

公开(公告)号：US20230221866A1

公开(公告)日：2023-07-13

申请号：US18000761

申请日：2021-05-20

Applicant: Arm Limited

Inventor： Jamshed JALAL ,  Gurunath RAMAGIRI ,  Tushar P RINGE ,  Mark David WERKHEISER ,  Ashok Kumar TUMMALA ,  Dimitrios KASERIDIS

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0653

Abstract: A technique for handling memory access requests is described. An apparatus has an interconnect for coupling a plurality of requester elements with a plurality of slave elements. The requester elements are arranged to issue memory access requests for processing by the slave elements. An intermediate element within the interconnect acts as a point of serialisation to order the memory access requests issued by requester elements via the intermediate element. The intermediate element has tracking circuitry for tracking handling of the memory access requests accepted by the intermediate element. Further, request acceptance management circuitry is provided to identify a target slave element amongst the plurality of slave elements for that given memory access request, and to determine whether the given memory access request is to be accepted by the intermediate element dependent on an indication of bandwidth capability for the target slave element.

公开(公告)号：US20170171095A1

公开(公告)日：2017-06-15

申请号：US14965237

申请日：2015-12-10

Applicant: ARM Limited

Inventor： Ramamoorthy Guru PRASADH ,  Jamshed JALAL ,  Ashok Kumar TUMMALA ,  Phanindra Kumar MANNAVA ,  Tushar P. RINGE

IPC: H04L12/891 ,  H04L12/835 ,  H04L29/06 ,  H04L12/26

CPC classification number: H04L47/41 ,  H04L43/106 ,  H04L43/16 ,  H04L47/30 ,  H04L69/08 ,  H04L69/18 ,  H04L69/22

Abstract: A bridging circuit and method of operation thereof, which couples first and second electronic circuits of a data processing system. The first electronic circuit generates signals corresponding to digits of a flow control unit (flit) of a first flow control protocol and where the second electronic circuit is responsive to signals corresponding to flits of a second flow control protocol. When first flits are destined for the same target buffer, they are combined to provide a second flit consistent with the second flow control protocol and transmitting the second flit to the second electronic circuit. The second flit includes data and metadata fields copied from the first flits, a common field common to each of the first flits, a merged field containing a merger of fields from the first flits and a validity field indicating which portions of the second flit contain valid data.

公开(公告)号：US20220283972A1

公开(公告)日：2022-09-08

申请号：US17189781

申请日：2021-03-02

Applicant: Arm Limited

Inventor： Ashok Kumar TUMMALA ,  Jamshed JALAL ,  Antony John HARRIS ,  Jeffrey Carl DEFILIPPI ,  Anitha KONA ,  Bruce James MATHEWSON

IPC: G06F13/38 ,  G06F13/40

Abstract: An apparatus and method are provided for handling protocol conversion. The apparatus has interconnect circuitry for routing messages between components coupled to the interconnect circuitry in a manner that conforms to a first communication protocol. Protocol conversion circuitry is coupled between the interconnect circuitry and an external communication path, for converting messages between the first communication protocol and a second communication protocol that has a layered architecture comprising multiple layers. The protocol conversion circuitry has a gateway component forming one of the components coupled to the interconnect circuitry, and a controller coupled with the gateway component and used to control connection with the external communication path. For a selected layer of the multiple layers, the protocol conversion circuitry provides, within the gateway component, upper selected layer circuitry to implement a first portion of functionality of the selected layer, where the first portion comprises at least protocol dependent functionality of the selected layer. It also provides, within the controller, lower selected layer circuitry to implement a remaining portion of the functionality of the selected layer, the remaining portion comprising only protocol independent functionality of the selected layer.

公开(公告)号：US20190340147A1

公开(公告)日：2019-11-07

申请号：US16027490

申请日：2018-07-05

Applicant: Arm Limited

Inventor： Jamshed JALAL ,  Tushar P. RINGE ,  Ashok Kumar TUMMALA ,  Gurunath RAMAGIRI

IPC: G06F13/42 ,  G06F15/173 ,  G06F12/0831

Abstract: A data processing network and method of operation thereof are provided for efficient transfer of ordered data from a Request Node to a target node. The Request Node send write requests to a Home Node and the Home Node responds to a first write request when resources have been allocated the Home Node. The Request Node then sends the data to the written. The Home Node also responds with a completion message when a coherency action has been performed at the Home Node. The Request Node acknowledges receipt of the completion message with a completion acknowledgement message that is not sent until completion messages have been received for all write requests older than the first write request for the ordered data, thereby maintaining data order. Following receipt of the completion acknowledgement for the first write request, the Home Node sends the data to be written to the target node.

公开(公告)号：US20170168876A1

公开(公告)日：2017-06-15

申请号：US15296283

申请日：2016-10-18

Applicant: ARM Limited

Inventor： Ashok Kumar TUMMALA ,  Jamshed JALAL ,  Paul Gilbert MEYER ,  Dimitrios KASERIDIS

IPC: G06F9/52 ,  G06F9/50

Abstract: A method, system, and device provide for the streaming of ordered requests from one or more Senders to one or more Receivers over an un-ordered interconnect while mitigating structural deadlock conditions.