公开(公告)号：US09374072B2

公开(公告)日：2016-06-21

申请号：US14268336

申请日：2014-05-02

Applicant: ARM Limited

Inventor： Betina Hold ,  Brian Cline ,  George Lattimore

IPC: H03K5/133 ,  H03K5/13

CPC classification number: H03K5/133

Abstract: An integrated circuit 2 includes a transistor 26 which has a normal switching speed arising during normal operations of that transistor that apply electrical signals within normal ranges. If it is desired to change the speed of operation of the transistor, then speed tuning circuitry 12 applies a tuning electrical signal with a tuning characteristic outside of the normal range of characteristics to the transistor concerned. The tuning electrical signal induces a change in at least one of the physical properties of that transistor such that when it resumes its modified normal operations the switching speed of that transistor will have changed. The tuning electrical signal may be a voltage (or current) outside of the normal range of voltages applied to the gate of a transistor so as to induce a permanent increase in the threshold of that transistor and so slow its speed of switching. Temperature of a transistor may also be controlled to induce a permanent change in performance/speed.

Abstract translation: 集成电路2包括晶体管26，其具有在该晶体管的正常操作期间产生正常切换速度，其在正常范围内施加电信号。 如果希望改变晶体管的操作速度，则速度调节电路12将具有超出正常特性范围的调谐特性的调谐电信号施加到相关的晶体管。 调谐电信号引起该晶体管的至少一个物理特性的变化，使得当其恢复其修改的正常操作时，该晶体管的开关速度将改变。 调谐电信号可以是在施加到晶体管的栅极的正常的电压范围之外的电压（或电流），以便引起该晶体管的阈值的永久增加，并因此降低其转换速度。 也可以控制晶体管的温度以引起性能/速度的永久性变化。

公开(公告)号：US08717084B1

公开(公告)日：2014-05-06

申请号：US13706718

申请日：2012-12-06

Applicant: ARM Limited

Inventor： Betina Hold ,  Brian Cline

IPC: H03K17/296

CPC classification number: H03K5/133

Abstract: An integrated circuit 2 includes a transistor 26 which has a normal switching speed arising during normal operations of that transistor that apply electrical signals within normal ranges. If it is desired to change the speed of operation of the transistor, then speed tuning circuitry 12 applies a tuning electrical signal with a tuning characteristic outside of the normal range of characteristics to the transistor concerned. The tuning electrical signal induces a change in at least one of the physical properties of that transistor such that when it resumes its modified normal operations the switching speed of that transistor will have changed. The tuning electrical signal may be a voltage (or current) outside of the normal range of voltages applied to the gate of a transistor so as to induce a permanent increase in the threshold of that transistor and so slow its speed of switching. Temperature of a transistor may also be controlled to induce a permanent change in performance/speed.

Abstract translation: 集成电路2包括晶体管26，其具有在该晶体管的正常操作期间产生正常切换速度，其在正常范围内施加电信号。 如果希望改变晶体管的操作速度，则速度调节电路12将具有超出正常特性范围的调谐特性的调谐电信号施加到相关的晶体管。 调谐电信号引起该晶体管的至少一个物理特性的变化，使得当其恢复其修改的正常操作时，该晶体管的开关速度将改变。 调谐电信号可以是施加到晶体管的栅极的正常电压范围之外的电压（或电流），以引起该晶体管的阈值的永久增加，并因此降低其转换速度。 也可以控制晶体管的温度以引起性能/速度的永久性变化。

公开(公告)号：US08995191B2

公开(公告)日：2015-03-31

申请号：US14026097

申请日：2013-09-13

Applicant: ARM Limited

Inventor： Betina Hold

IPC: G11C7/08 ,  G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G06F11/10 ,  G11C29/04

CPC classification number: G11C7/08 ,  G06F11/1048 ,  G11C7/06 ,  G11C7/1006 ,  G11C7/22 ,  G11C2029/0411

Abstract: A memory includes an array of memory cells with each memory cell coupled to an associated pair of bit lines. Read control circuitry is configured to activate a number of addressed memory cells in order to couple each addressed memory cell to its associated pair of bit lines. Sense amplifier circuitry is then coupled to the bit lines to determine the data value stored in each addressed memory. In a speculative read mode of operation, the sense amplifier circuitry evaluates the differential signals. Error detection circuitry is then used to capture the differential signals on the associated pair of bit lines for each addressed memory cell, and to apply an error detection operation to determine if the differential signals as evaluated by the sense amplifier circuitry had not developed to the necessary degree and, in that event, an error signal is asserted.

Abstract translation: 存储器包括存储器单元的阵列，每个存储器单元耦合到相关联的位线对。 读控制电路被配置为激活多个寻址的存储器单元，以便将每个寻址的存储器单元耦合到其相关联的位线对。 然后将感测放大器电路耦合到位线以确定存储在每个寻址的存储器中的数据值。 在推测读取操作模式中，读出放大器电路评估差分信号。 然后使用错误检测电路来捕获每个寻址的存储器单元的相关的位线对上的差分信号，并且应用错误检测操作来确定由感测放大器电路评估的差分信号是否没有发展到必要 在这种情况下，会产生一个错误信号。

公开(公告)号：US20140016419A1

公开(公告)日：2014-01-16

申请号：US14026097

申请日：2013-09-13

Applicant: ARM LIMITED

Inventor： Betina Hold

IPC: G11C7/08

CPC classification number: G11C7/08 ,  G06F11/1048 ,  G11C7/06 ,  G11C7/1006 ,  G11C7/22 ,  G11C2029/0411

Abstract: A memory includes an array of memory cells with each memory cell coupled to an associated pair of bit lines. Read control circuitry is configured to activate a number of addressed memory cells in order to couple each addressed memory cell to its associated pair of bit lines. Sense amplifier circuitry is then coupled to the bit lines to determine the data value stored in each addressed memory. In a speculative read mode of operation, the sense amplifier circuitry evaluates the differential signals. Error detection circuitry is then used to capture the differential signals on the associated pair of bit lines for each addressed memory cell, and to apply an error detection operation to determine if the differential signals as evaluated by the sense amplifier circuitry had not developed to the necessary degree and, in that event, an error signal is asserted.

Abstract translation: 存储器包括存储器单元的阵列，每个存储器单元耦合到相关联的位线对。 读控制电路被配置为激活多个寻址的存储器单元，以便将每个寻址的存储器单元耦合到其相关联的位线对。 然后将感测放大器电路耦合到位线以确定存储在每个寻址的存储器中的数据值。 在推测读取操作模式中，读出放大器电路评估差分信号。 然后使用错误检测电路来捕获每个寻址的存储器单元的相关位线对上的差分信号，并且应用错误检测操作来确定由感测放大器电路评估的差分信号是否没有发展到必要 在这种情况下，会产生一个错误信号。