公开(公告)号：US20210089323A1

公开(公告)日：2021-03-25

申请号：US16950936

申请日：2020-11-18

Applicant: ARM Limited

Inventor： Jatin BHARTIA ,  Kauser Yakub JOHAR ,  Antony John Penton

IPC: G06F9/38 ,  G06F9/30

Abstract: A processing system 2 includes a processing pipeline 12, 14, 16, 18, 28 which includes fetch circuitry 12 for fetching instructions to be executed from a memory 6, 8. Buffer control circuitry 34 is responsive to a programmable trigger, such as explicit hint instructions delimiting an instruction burst, or predetermined configuration data specifying parameters of a burst together with a synchronising instruction, to trigger the buffer control circuitry to stall a stallable portion of the processing pipeline (e.g. issue circuitry 16), to accumulate within one or more buffers 30, 32 fetched instructions starting from a predetermined starting instruction, and, when those instructions have been accumulated, to restart the stallable portion of the pipeline.

公开(公告)号：US20180357065A1

公开(公告)日：2018-12-13

申请号：US15974769

申请日：2018-05-09

Applicant: Arm Limited

Inventor： Jatin BHARTIA ,  Kauser Yakub JOHAR ,  Antony John Penton

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3867 ,  G06F9/30079

Abstract: A processing system 2 includes a processing pipeline 12, 14, 16, 18, 28 which includes fetch circuitry 12 for fetching instructions to be executed from a memory 6, 8. Buffer control circuitry 34 is responsive to a programmable trigger, such as explicit hint instructions delimiting an instruction burst, or predetermined configuration data specifying parameters of a burst together with a synchronising instruction, to trigger the buffer control circuitry to stall a stallable portion of the processing pipeline (e.g. issue circuitry 16), to accumulate within one or more buffers 30, 32 fetched instructions starting from a predetermined starting instruction, and, when those instructions have been accumulated, to restart the stallable portion of the pipeline.

公开(公告)号：US20240338323A1

公开(公告)日：2024-10-10

申请号：US18295866

申请日：2023-04-05

Applicant: Arm Limited

Inventor： Eric Ola Harald LILJEDAHL ,  Jatin BHARTIA

IPC: G06F12/12 ,  G06F12/0891

CPC classification number: G06F12/12 ,  G06F12/0891

Abstract: An apparatus with an additional storage element or field is provided where a subscription indicator is stored, indicating a subscription to a region of memory, and hence subscribing to a cache line corresponding to the region of memory. In response to a subscribed cache line being invalidated, the apparatus performs actions to re-fetch the cache line, and to store the cache line in the cache after a short delay. The subscription indicator may be stored in a variety of ways, and may include further information that influences the functionality of the present techniques. Such further information may be adjustable in order to dynamically control the functionality of the disclosed techniques for a particular implementation over time.

公开(公告)号：US20230385066A1

公开(公告)日：2023-11-30

申请号：US17752060

申请日：2022-05-24

Applicant: Arm Limited

Inventor： Houdhaifa BOUZGUARROU ,  Michael Brian SCHINZLER ,  Yasuo ISHII ,  Jatin BHARTIA ,  Sumanth CHENGAD RAGHU

IPC: G06F9/38 ,  G06F1/03

CPC classification number: G06F9/3848 ,  G06F9/3844 ,  G06F9/3806 ,  G06F1/03

Abstract: A first type of prediction, for controlling execution of at least one instruction by processing circuitry, is based at least on a first prediction table storing prediction information looked up based on at least a first portion of branch history information stored in branch history storage corresponding to a first predetermined number of branches. In response to detecting an execution state switch of the processing circuitry from a first execution state to a second, more privileged, execution state, use of the first prediction table for determining the first type of prediction is disabled. In response to detecting that a number of branches causing an update to the branch history storage since the execution state switch is greater than or equal to the first predetermined number, use of the first prediction table in determining the first type of prediction is re-enabled.

公开(公告)号：US20230205537A1

公开(公告)日：2023-06-29

申请号：US17560643

申请日：2021-12-23

Applicant: Arm Limited

Inventor： Adrian Viorel POPESCU ,  Remus-Gabriel VULTUR ,  Jatin BHARTIA

IPC: G06F9/38

CPC classification number: G06F9/382 ,  G06F9/3802

Abstract: Aspects of the present disclosure relate to an apparatus comprising fetch circuitry. The fetch circuitry comprises a pointer-based fetch queue for queuing processing instructions retrieved from a storage, and pointer storage for storing a pointer identifying a current fetch queue element. The apparatus comprises decode circuitry having a plurality of decode units, and fetch queue extraction circuitry to, based on the pointer, extract the content of a plurality of elements of the fetch queue; apply combinatorial logic to speculatively produce, from the content of said fetch queue entries, a plurality of speculative potential instructions; and transmit each speculative potential instruction to a corresponding one of said decode units. Each decode unit is configured to decode the corresponding speculative potential instruction. The instruction extraction circuitry is configured to extract a subset of said plurality of speculative potential instructions, and transmit said determined subset to pipeline component circuitry.