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公开(公告)号：US20210089323A1
公开(公告)日：2021-03-25
申请号：US16950936
申请日：2020-11-18
Applicant: ARM Limited
Inventor： Jatin BHARTIA , Kauser Yakub JOHAR , Antony John Penton
Abstract: A processing system 2 includes a processing pipeline 12, 14, 16, 18, 28 which includes fetch circuitry 12 for fetching instructions to be executed from a memory 6, 8. Buffer control circuitry 34 is responsive to a programmable trigger, such as explicit hint instructions delimiting an instruction burst, or predetermined configuration data specifying parameters of a burst together with a synchronising instruction, to trigger the buffer control circuitry to stall a stallable portion of the processing pipeline (e.g. issue circuitry 16), to accumulate within one or more buffers 30, 32 fetched instructions starting from a predetermined starting instruction, and, when those instructions have been accumulated, to restart the stallable portion of the pipeline.
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公开(公告)号：US20170346504A1
公开(公告)日：2017-11-30
申请号：US15587429
申请日：2017-05-05
Applicant: ARM Limited
Inventor： Kauser Yakub JOHAR
CPC classification number: H03M13/05 , G06F11/1016 , H03M13/616
Abstract: An apparatus and method are provided for generating an error code for a block comprising a plurality of data bits and a plurality of address bits. The apparatus has block generation circuitry to generate a block comprising a plurality of data bits and a plurality of address bits, and error code generation circuitry for receiving that block and a mask array comprising a plurality of mask rows, and for then applying an error code generation algorithm to generate an error code for the block. The error code comprises a plurality of check bits, where each check bit is determined using the block and a corresponding mask row of the mask array. Each mask row comprises a plurality of mask bits, each mask bit being associated with a corresponding bit of the block. At least one mask row has its mask bit values constrained so as to ensure that when all of the data bits of the block have the same value, the error code generated by the error code generation circuitry has at least one check bit having a different value to the value of the data bits irrespective of the value of the address bits. In addition to supporting detection and/or correction of errors in the data bits, such an approach also allows memory address decode errors to be detected whilst in addition allowing detection of stuck at zero or stuck at one errors in a memory's output.
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公开(公告)号：US20160321137A1
公开(公告)日：2016-11-03
申请号：US15073807
申请日：2016-03-18
Applicant: ARM LIMITED
Inventor： Michele RIGA , Kauser Yakub JOHAR
CPC classification number: G06F11/1076 , G06F11/1012 , H03M13/13 , H03M13/2906 , H03M13/35 , H03M13/356 , H03M13/618 , H03M13/6368
Abstract: An error protection key generation method and system are provided, the method being used to generate a key for use in computing an error protection code for an input data value according to a chosen error protection scheme. The method comprises inputting a plurality of desired data value sizes, and then applying a key generation algorithm to generate a key for use in computing the error protection code for a maximum data value size amongst the plurality of data value sizes. The key generation algorithm is arranged so that it generates the key so as to comprise a plurality of sub-keys, where each sub-key is associated with one of the input data value sizes, and where each sub-key conforms to a key requirement of the error protection scheme. As a result, a generic key is produced containing a plurality of sub-keys, where each sub-key is associated with a particular desired data value size, and can be extracted and used independently given that each sub-key conforms to the error protection scheme requirements. This provides significant benefits in the design and verification of error protection circuits using such keys.
Abstract translation: 提供了一种错误保护密钥生成方法和系统，该方法用于根据选择的错误保护方案生成用于计算输入数据值的错误保护代码的密钥。 该方法包括输入多个期望的数据值大小，然后应用密钥生成算法来生成用于计算多个数据值大小中的最大数据值大小的错误保护代码的密钥。 密钥生成算法被布置为使得其生成密钥以便包括多个子密钥，其中每个子密钥与输入数据值大小之一相关联，并且其中每个子密钥符合密钥要求 的错误保护方案。 结果，产生包含多个子密钥的通用密钥，其中每个子密钥与特定的所需数据值大小相关联，并且可以独立地提取和使用，因为每个子密钥都符合错误保护 方案要求。 这在使用这种键的误差保护电路的设计和验证中提供了显着的益处。
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Patent Agency Ranking
公开(公告)号：US20160139922A1
公开(公告)日：2016-05-19
申请号：US14930920
申请日：2015-11-03
Applicant: ARM LIMITED
Inventor： Simon John CRASKE , Alexander Alfred Hornung , Max John BATLEY , Kauser Yakub JOHAR
CPC classification number: G06F9/30072 , G06F9/30087 , G06F9/3834 , G06F9/45533 , G06F9/522
Abstract: Apparatus for data processing and a method of data processing are provided, according to which the processing circuitry of the apparatus can access a memory system and execute data processing instructions in one context of multiple contexts which it supports. When the processing circuitry executes a barrier instruction, the resulting access ordering constraint may be limited to being enforced for accesses which have been initiated by the processing circuitry when operating in an identified context, which may for example be the context in which the barrier instruction has been executed. This provides a separation between the operation of the processing circuitry in its multiple possible contexts and in particular avoids delays in the completion of the access ordering constraint, for example relating to accesses to high latency regions of memory, from affecting the timing sensitivities of other contexts.
Abstract translation: 提供了用于数据处理的装置和数据处理方法，根据该装置，该装置的处理电路可以访问存储器系统并在其支持的多个上下文的一个上下文中执行数据处理指令。 当处理电路执行屏障指令时，所得到的访问排序约束可以被限制为对于在所识别的上下文中操作时由处理电路启动的访问被强制执行，其可以例如是屏障指令具有的上下文 被执行 这提供了处理电路在其多个可能上下文中的操作之间的间隔，并且特别地避免了访问排序约束的完成中的延迟，例如涉及对存储器的高等待时间区域的访问，从而影响其他上下文的定时灵敏度 。
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公开(公告)号：US20170293541A1
公开(公告)日：2017-10-12
申请号：US15447673
申请日：2017-03-02
Applicant: ARM Limited
Inventor： Balaji VENU , Kauser Yakub JOHAR , Marco BONINO
IPC: G06F11/22 , G06F11/273 , G06F11/27
CPC classification number: G06F11/27 , G06F11/0721 , G06F11/0766 , G06F11/0775 , G06F11/0784 , G06F11/22 , G06F11/2236 , G06F11/2242 , G06F11/2284 , G06F11/24 , G06F11/273
Abstract: Apparatus and a method for processor core self-testing are disclosed. The apparatus comprises processor core circuitry to perform data processing operations by executing data processing instructions. Separate self-test control circuitry causes the processor core circuitry to temporarily switch from a first state of executing the data processing instructions to a second state of executing a self-test sequence of instructions, before returning to the first state of executing the data processing instructions without a reboot of the processor core circuitry being required. There is also self-test support circuitry, wherein the processor core circuitry is responsive to the self-test sequence of instructions to cause an export of at least one self-test data item via the self-test support circuitry to the self-test control circuitry.
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公开(公告)号：US20170286116A1
公开(公告)日：2017-10-05
申请号：US15432121
申请日：2017-02-14
Applicant: ARM Limited
Inventor： Kauser Yakub JOHAR , Antony John PENTON
IPC: G06F9/30
CPC classification number: G06F9/3005 , G06F9/30054 , G06F9/324 , G06F9/3804 , G06F9/3867
Abstract: A data processing apparatus has prefetch circuitry for prefetching instructions from a data store into an instruction queue. Branch prediction circuitry is provided for predicting outcomes of branch instructions and the prefetch circuitry may prefetch instructions subsequent to the branch based on the predicted outcome. Instruction identifying circuitry identifies whether a given instruction prefetched from the data store is a predetermined type of program flow altering instruction and if so then controls the prefetch circuitry to halt prefetching of subsequent instructions into the instruction queue.
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公开(公告)号：US20210089381A1
公开(公告)日：2021-03-25
申请号：US16580045
申请日：2019-09-24
Applicant: Arm Limited
Inventor： Kauser Yakub JOHAR , Loïc PIERRON
Abstract: An apparatus is described comprising a cluster of processing elements. The cluster having a split mode in which the processing elements are configured to process independent processing workloads, and a lock mode in which the processing elements comprise at least one primary processing element and at least one redundant processing element, each redundant processing element configured to perform a redundant processing workload for checking correctness of a primary processing workload performed by the primary processing element. Each processing element has an associated local memory comprising a plurality of memory locations. A local memory access control mechanism is configured, during the lock mode, to allow the at least one primary processing element to access memory locations within the local memory associated with the at least one redundant processing element
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公开(公告)号：US20180357065A1
公开(公告)日：2018-12-13
申请号：US15974769
申请日：2018-05-09
Applicant: Arm Limited
Inventor： Jatin BHARTIA , Kauser Yakub JOHAR , Antony John Penton
CPC classification number: G06F9/3867 , G06F9/30079
Abstract: A processing system 2 includes a processing pipeline 12, 14, 16, 18, 28 which includes fetch circuitry 12 for fetching instructions to be executed from a memory 6, 8. Buffer control circuitry 34 is responsive to a programmable trigger, such as explicit hint instructions delimiting an instruction burst, or predetermined configuration data specifying parameters of a burst together with a synchronising instruction, to trigger the buffer control circuitry to stall a stallable portion of the processing pipeline (e.g. issue circuitry 16), to accumulate within one or more buffers 30, 32 fetched instructions starting from a predetermined starting instruction, and, when those instructions have been accumulated, to restart the stallable portion of the pipeline.
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