公开(公告)号：US20210091041A1

公开(公告)日：2021-03-25

申请号：US16580349

申请日：2019-09-24

Applicant: Arm Limited

Inventor： Saurabh Pijuskumar SINHA ,  Joel Thornton IRBY ,  Supreet JELOKA

IPC: H01L25/065 ,  H01L23/367 ,  H01L21/66 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00

Abstract: A three-dimensional (3D) integrated circuit (IC) can include a bottom tier with first circuitry and first backside TSVs coupled to a substrate; a top tier coupled to the first tier at a front side and having second circuitry and second backside TSVs; and a heat conductor on the second backside TSVs of the top tier. The heat conductor is coupled to the second backside TSVs to provide improved heat dissipation through the top tier. During pre-bond testing, the top tier can be tested at speed using the second backside TSVs.

公开(公告)号：US20210133027A1

公开(公告)日：2021-05-06

申请号：US16669906

申请日：2019-10-31

Applicant: Arm Limited

Inventor： Joel Thornton IRBY ,  Wendy Arnott ELSASSER ,  Mudit BHARGAVA ,  Yew Keong CHONG ,  George McNeil LATTIMORE ,  James Dennis DODRILL

IPC: G06F11/10 ,  G06N20/00 ,  G11C7/10 ,  G11C5/14

Abstract: A system-on-chip is provided that includes functional circuitry that performs a function. Control circuitry controls the function based one or more configuration parameters. Non-volatile storage circuitry includes a plurality of non-volatile storage cells each being adapted to write at least a bit of the one or more configuration parameters in a rewritable, persistent manner a plurality of times. Read circuitry locally accesses the non-volatile storage circuitry, obtains the one or more configuration parameters from the non-volatile storage circuitry and provides the one or more configuration parameters to the control circuitry. Write circuitry obtains the one or more configuration parameters and provides the one or more configuration parameters to the non-volatile storage circuitry by locally accessing the non-volatile storage circuitry.

公开(公告)号：US20180150389A1

公开(公告)日：2018-05-31

申请号：US15361804

申请日：2016-11-28

Applicant: ARM Limited

Inventor： Mudit BHARGAVA ,  Joel Thornton IRBY ,  Vikas CHANDRA

IPC: G06F12/02 ,  H04L9/32

Abstract: A method and apparatus is provided for wear leveling of a storage medium in an electronic device. Wear leveling is achieved by mapping each logical memory address to a corresponding physical memory address. The mapping information is consistent over an on-period of a power cycle, but changes from one power cycle to another. The mapping information, such as a key value for example, may be stored in non-volatile memory such as, for example, a correlated electron random switch (CES) storage element. The mapping may be obtained by manipulating bits of the logical address to obtain the physical address.