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公开(公告)号：US20170046281A1
公开(公告)日：2017-02-16
申请号：US15335479
申请日：2016-10-27
Applicant: ARM LIMITED
Inventor： Vikas CHANDRA , Robert Campbell AITKEN
CPC classification number: G06F12/1408 , G06F21/72 , G06F21/79 , G06F2212/1052 , G06F2212/402 , G09C1/00 , H04L9/0861 , H04L9/0866 , H04L2209/12
Abstract: Encryption of data within a memory is provided by key generation circuitry which serves to generate a key as a function of the address within the memory being accessed and then encryption circuitry or decryption circuitry which serve respectively to encrypt or decrypt the data as a function of the key that has been generated based upon the address. The encryption and the decryption may be performed using a bitwise XOR operation. The key generation circuitry may have the form of physically unclonable function circuitry, which varies from instance to instance of implementation and that operates to generate the same key for the same address upon both write and read operations within the same instance.
Abstract translation: 由存储器内的地址的函数产生密钥的密钥生成电路提供存储器内的数据加密，然后分别用于加密或解密数据作为函数的加密电路或解密电路 基于地址生成的密钥。 可以使用按位异或运算来执行加密和解密。 密钥生成电路可以具有物理上不可克隆的功能电路的形式，其从实例到实现实例变化，并且在相同的实例中的写入和读取操作两者之间，为同一地址生成相同的密钥。
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公开(公告)号：US20150269982A1
公开(公告)日：2015-09-24
申请号：US14219498
申请日：2014-03-19
Applicant: ARM LIMITED
Inventor： Vikas CHANDRA , Peter BESHAY
CPC classification number: G11C7/22 , G11C8/08 , G11C11/41 , G11C11/418 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/24 , G11C2029/1202
Abstract: Apparatus for storing data and a method of adapting a duration of a wordline pulse in an apparatus for storing data are provided. Sensor circuitry comprises a calibrated bitcell which is calibrated to use a duration of wordline pulse which matches a longest wordline pulse required by any bitcell in an array of bitcells for a successful write operation to be carried out. The duration of wordline pulse is signalled to wordline pulse circuitry, which generates a wordline pulse for the array of bitcells with this wordline pulse duration. The sensor circuitry is configured to adapt the wordline pulse duration in dependence on current local conditions in which the apparatus operates to compensate for influence of the current local conditions on the longest wordline pulse required by any bitcell in the array of bitcells.
Abstract translation: 提供了用于存储数据的装置和在用于存储数据的装置中适应字线脉冲的持续时间的方法。 传感器电路包括校准的位单元，其经校准以使用字线脉冲的持续时间，其与位单元阵列中的任何位单元所需的最长字线脉冲匹配，以执行成功的写操作。 字线脉冲的持续时间被发送到字线脉冲电路，该线路脉冲电路利用该字线脉冲持续时间产生用于位单元阵列的字线脉冲。 传感器电路被配置为根据当前本地条件来适应字线脉冲持续时间，其中设备操作以补偿当前局部条件对位单元阵列中任何位单元所需的最长字线脉冲的影响。
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公开(公告)号：US20140143291A1
公开(公告)日：2014-05-22
申请号：US13678621
申请日：2012-11-16
Applicant: ARM LIMITED
Inventor： Sachin Satish IDGUNJI , Vikas CHANDRA
IPC: G06F7/58
Abstract: A storage circuit 2 in the form of a master slave latch includes a slave stage 6 serving as a bit storage circuit. The slave stage 6 includes an inverter chain which when operating in a normal mode includes an even number of inverters 10, 12 and when operating in an random number generation mode includes an odd number of inverters 10, 12, 14 and so functions as a free running ring oscillator. When a switch is made back from the random number generation mode to the normal mode, then the oscillation ceases and a stable pseudo random bit value is output from the bit value storage circuit 6.
Abstract translation: 主从锁存器形式的存储电路2包括用作位存储电路的从级6。 从动级6包括一个逆变器链，当在正常模式下操作时包括偶数个反相器10,12，并且当以随机数生成模式操作时，包括奇数个反相器10,12,14等作为自由 运行环形振荡器。 当从随机数生成模式切换回正常模式时，停止振荡，并从位值存储电路6输出稳定的伪随机比特值。
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公开(公告)号：US20160078999A1
公开(公告)日：2016-03-17
申请号：US14488647
申请日：2014-09-17
Applicant: ARM Limited
Inventor： Lucian SHIFREN , Vikas CHANDRA , Mudit BHARGAVA
CPC classification number: H01G4/005 , G09C1/00 , H01C1/14 , H01C7/006 , H01C17/00 , H01C17/06586 , H01G4/08 , H01G4/14 , H01G4/33 , H04L9/0866 , H04L2209/12
Abstract: An electrical component is formed with a directed self assembly portion having a random electrical characteristic, such as resistance or capacitance. The random pattern can be produced by using a directed self assembly polymer with guide structures 2 including randomness inducing features. The electrical components with the random electrical characteristics may be used in electrical circuits relying upon random variation in electrical characteristics, such as physically unclonable function circuitry. The electrical components may be resistors and/or capacitors.
Abstract translation: 电气部件形成有具有诸如电阻或电容等随机电特性的定向自组装部分。 可以通过使用包括随机诱导特征的引导结构2的定向自组装聚合物来生产随机图案。 具有随机电特性的电气部件可以用于依赖于电特性随机变化的电路中，例如物理上不可克隆的功能电路。 电气部件可以是电阻器和/或电容器。
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公开(公告)号：US20160078252A1
公开(公告)日：2016-03-17
申请号：US14486181
申请日：2014-09-15
Applicant: ARM LIMITED
Inventor： Vikas CHANDRA , Robert Campbell AITKEN
CPC classification number: G06F12/1408 , G06F21/72 , G06F21/79 , G06F2212/1052 , G06F2212/402 , G09C1/00 , H04L9/0861 , H04L9/0866 , H04L2209/12
Abstract: Encryption of data within a memory 6 is provided by key generation circuitry 12 which serves to generate a key as a function of the address within the memory 6 being accessed and then encryption circuitry 14 or decryption circuitry 16 which serve respectively to encrypt or decrypt the data as a function of the key that has been generated based upon the address. The encryption and the decryption may be performed using a bitwise XOR operation. The key generation circuitry may have the form of physically unclonable function circuitry, which varies from instance to instance of implementation and that operates to generate the same key for the same address upon both write and read operations within the same instance.
Abstract translation: 存储器6内的数据加密由密钥生成电路12提供，该密钥生成电路12用于生成作为被访问的存储器6内的地址的函数的密钥，然后分别用于加密或解密数据的加密电路14或解密电路16 作为基于地址生成的密钥的函数。 可以使用按位异或运算来执行加密和解密。 密钥生成电路可以具有物理上不可克隆的功能电路的形式，其从实例到实现实例变化，并且在相同的实例中的写入和读取操作两者之间，为同一地址生成相同的密钥。
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Patent Agency Ranking
公开(公告)号：US20180173899A1
公开(公告)日：2018-06-21
申请号：US15381222
申请日：2016-12-16
Applicant: ARM Limited
Inventor： Vikas CHANDRA , Mudit BHARGAVA
CPC classification number: G06F21/72 , G06F21/75 , G06F21/76 , G06F2221/2123 , G09C1/06 , H03K19/17768 , H04L9/003 , H04L9/06
Abstract: A protected circuit includes a logic circuit having one or more input nodes and one or more output nodes. The logic circuit has a network of logic elements and one or more logic encryption elements. A logic encryption element includes a memory cell, such as a correlated electron switch for example, coupled with a configurable sub-circuit that is configured by a value stored in the memory cell to encrypt a signal or a signal path. A mapping of values at the one or more input nodes to values at the one or more output nodes corresponds to a desired mapping when values stored in the one or more memory cells match component values of a prescribed key vector. The memory cells may be programmed after fabrication of the circuit.
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公开(公告)号：US20150363267A1
公开(公告)日：2015-12-17
申请号：US14306697
申请日：2014-06-17
Applicant: ARM Limited
Inventor： Vikas CHANDRA , Robert Campbell AITKEN
IPC: G06F11/10
CPC classification number: G06F11/1076 , G01R31/3185 , G01R31/318516 , G01R31/318519 , G01R31/318541 , G01R31/318544 , G01R31/318558 , G01R31/318561 , G01R31/3187 , G06F1/08 , G06F11/0727 , G06F11/0751 , G06F11/10 , G06F11/1008 , G06F11/1032 , G06F11/1048 , G11C11/419
Abstract: A data storage apparatus is provided which has a plurality of data storage units, each respective data storage unit configured to store a respective data bit of a data word. Stored data value parity generation circuitry is configured to generate a parity bit for the data word in dependence on the data bits of the data word stored in the plurality of data storage units. The stored data value parity generation circuitry is configured such that switching within the stored data value parity generation circuitry does not occur when the data word is read out from the plurality of data storage units. Transition detection circuitry is configured to detect a change in value of the parity bit.
Abstract translation: 提供一种具有多个数据存储单元的数据存储装置，每个数据存储单元被配置为存储数据字的相应数据位。 存储的数据值奇偶校验生成电路被配置为根据存储在多个数据存储单元中的数据字的数据位产生数据字的奇偶校验位。 存储的数据值奇偶校验生成电路被配置为使得当从多个数据存储单元读出数据字时，不会发生存储的数据值奇偶校验生成电路内的切换。 转换检测电路被配置为检测奇偶校验位的值的变化。
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公开(公告)号：US20180150389A1
公开(公告)日：2018-05-31
申请号：US15361804
申请日：2016-11-28
Applicant: ARM Limited
Inventor： Mudit BHARGAVA , Joel Thornton IRBY , Vikas CHANDRA
Abstract: A method and apparatus is provided for wear leveling of a storage medium in an electronic device. Wear leveling is achieved by mapping each logical memory address to a corresponding physical memory address. The mapping information is consistent over an on-period of a power cycle, but changes from one power cycle to another. The mapping information, such as a key value for example, may be stored in non-volatile memory such as, for example, a correlated electron random switch (CES) storage element. The mapping may be obtained by manipulating bits of the logical address to obtain the physical address.
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9.发明申请INTEGRATED CIRCUIT DEVICE COMPRISING ENVIRONMENT-HARDENED DIE AND LESS-ENVIRONMENT-HARDENED DIE 审中-公开集成电路设备，包括环境硬化和环境恶化的DIE公开(公告)号：US20160161550A1
公开(公告)日：2016-06-09
申请号：US14560755
申请日：2014-12-04
Applicant: ARM Limited
Inventor： Gregory Munson YERIC , Vikas CHANDRA
IPC: G01R31/28 , H01L25/065 , H01L21/66
CPC classification number: G01R31/2855 , G01R31/2856 , H01L22/30 , H01L22/34 , H01L25/0657 , H01L2224/48091 , H01L2224/48145 , H01L2224/73204 , H01L2225/06541 , H01L2225/06589 , H01L2225/06596 , H01L2924/0002 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
Abstract: An integrated circuit device has at least one environment-hardened die and at least one less-environment-hardened die. Environment-hardened circuitry on the environment-hardened die is more resistant to the degradation when exposed to a predetermined environmental condition than the less-environment-hardened circuitry on the environment-hardened die. The dice are combined using a 3D or 2.5D integrated circuit technology. This is very useful for testing circuits at adverse environmental conditions (e.g. high temperature), or for providing circuits to operate at such conditions.
Abstract translation: 集成电路装置具有至少一个环境硬化的模具和至少一个较少环境硬化的模具。 环境硬化的模具上的环境硬化电路在暴露于预定的环境条件下比在环境硬化的模具上的环境硬化较差的电路更能抵抗劣化。 骰子使用3D或2.5D集成电路技术进行组合。 这对于在不利的环境条件（例如高温）下的测试电路或在这种情况下提供电路进行操作非常有用。
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公开(公告)号：US20150363268A1
公开(公告)日：2015-12-17
申请号：US14306714
申请日：2014-06-17
Applicant: ARM Limited
Inventor： Vikas CHANDRA , Robert Campbell Aitken
IPC: G06F11/10
CPC classification number: G06F11/1076 , G06F11/0727 , G06F11/0751
Abstract: An apparatus has a plurality of storage units. A parity generator is configured to generate a parity value in dependence on the respective values stored in the plurality of storage units. The parity generator is configured such that determination of the parity value is independent of a read access to the data stored the plurality of storage units. A detector is configured to detect a change in value of the parity value.
Abstract translation: 一种装置具有多个存储单元。 奇偶校验发生器被配置为根据存储在多个存储单元中的相应值产生奇偶校验值。 奇偶校验发生器被配置为使得奇偶校验值的确定与存储多个存储单元的数据的读访问无关。 检测器被配置为检测奇偶校验值的值的变化。
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