公开(公告)号：US20160078999A1

公开(公告)日：2016-03-17

申请号：US14488647

申请日：2014-09-17

Applicant: ARM Limited

Inventor： Lucian SHIFREN ,  Vikas CHANDRA ,  Mudit BHARGAVA

IPC: H01G4/005 ,  H01C1/14 ,  H01C17/00

CPC classification number: H01G4/005 ,  G09C1/00 ,  H01C1/14 ,  H01C7/006 ,  H01C17/00 ,  H01C17/06586 ,  H01G4/08 ,  H01G4/14 ,  H01G4/33 ,  H04L9/0866 ,  H04L2209/12

Abstract: An electrical component is formed with a directed self assembly portion having a random electrical characteristic, such as resistance or capacitance. The random pattern can be produced by using a directed self assembly polymer with guide structures 2 including randomness inducing features. The electrical components with the random electrical characteristics may be used in electrical circuits relying upon random variation in electrical characteristics, such as physically unclonable function circuitry. The electrical components may be resistors and/or capacitors.

Abstract translation: 电气部件形成有具有诸如电阻或电容等随机电特性的定向自组装部分。 可以通过使用包括随机诱导特征的引导结构2的定向自组装聚合物来生产随机图案。 具有随机电特性的电气部件可以用于依赖于电特性随机变化的电路中，例如物理上不可克隆的功能电路。 电气部件可以是电阻器和/或电容器。

公开(公告)号：US20180173899A1

公开(公告)日：2018-06-21

申请号：US15381222

申请日：2016-12-16

Applicant: ARM Limited

Inventor： Vikas CHANDRA ,  Mudit BHARGAVA

IPC: G06F21/72 ,  H04L9/06 ,  H04L9/00

CPC classification number: G06F21/72 ,  G06F21/75 ,  G06F21/76 ,  G06F2221/2123 ,  G09C1/06 ,  H03K19/17768 ,  H04L9/003 ,  H04L9/06

Abstract: A protected circuit includes a logic circuit having one or more input nodes and one or more output nodes. The logic circuit has a network of logic elements and one or more logic encryption elements. A logic encryption element includes a memory cell, such as a correlated electron switch for example, coupled with a configurable sub-circuit that is configured by a value stored in the memory cell to encrypt a signal or a signal path. A mapping of values at the one or more input nodes to values at the one or more output nodes corresponds to a desired mapping when values stored in the one or more memory cells match component values of a prescribed key vector. The memory cells may be programmed after fabrication of the circuit.

公开(公告)号：US20160180896A1

公开(公告)日：2016-06-23

申请号：US14581229

申请日：2014-12-23

Applicant: ARM Limited

Inventor： Gus YEUNG ,  Fakhruddin Ali BOHRA ,  Mudit BHARGAVA ,  Andy Wangkun CHEN ,  Yew Keong CHONG

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/12

CPC classification number: G11C7/1012 ,  G11C7/12 ,  G11C7/22

Abstract: A memory 2 includes a regular array of storage elements 4. A regular array of write multiplexers 8 is provided outside of the regular array of storage elements 4. The storage element pitch is matched to the write multiplexer pitch. The write multiplexers 10 support a plurality of write ports. When forming a memory design 2, a given instance of an array of write multiplexers 8 may be selected in dependence upon the desired number of write ports to support and this combined with a common form of storage element array 4.

Abstract translation: 存储器2包括存储元件4的规则阵列。写入多路复用器8的规则阵列被提供在存储元件4的规则阵列之外。存储元件间距与写多路复用器间距匹配。 写多路复用器10支持多个写端口。 当形成存储器设计2时，可以根据要支持的写入端口的期望数量来选择写入多路复用器8的阵列的给定实例，并且与常规形式的存储元件阵列4组合。

公开(公告)号：US20210133027A1

公开(公告)日：2021-05-06

申请号：US16669906

申请日：2019-10-31

Applicant: Arm Limited

Inventor： Joel Thornton IRBY ,  Wendy Arnott ELSASSER ,  Mudit BHARGAVA ,  Yew Keong CHONG ,  George McNeil LATTIMORE ,  James Dennis DODRILL

IPC: G06F11/10 ,  G06N20/00 ,  G11C7/10 ,  G11C5/14

Abstract: A system-on-chip is provided that includes functional circuitry that performs a function. Control circuitry controls the function based one or more configuration parameters. Non-volatile storage circuitry includes a plurality of non-volatile storage cells each being adapted to write at least a bit of the one or more configuration parameters in a rewritable, persistent manner a plurality of times. Read circuitry locally accesses the non-volatile storage circuitry, obtains the one or more configuration parameters from the non-volatile storage circuitry and provides the one or more configuration parameters to the control circuitry. Write circuitry obtains the one or more configuration parameters and provides the one or more configuration parameters to the non-volatile storage circuitry by locally accessing the non-volatile storage circuitry.

公开(公告)号：US20180212582A1

公开(公告)日：2018-07-26

申请号：US15410922

申请日：2017-01-20

Applicant: ARM Limited

Inventor： Bal S. SANDHU ,  Mudit BHARGAVA ,  Akshay KUMAR ,  Piyush AGARWAL ,  Shidhartha DAS

IPC: H03H7/065

CPC classification number: H03H7/065 ,  H01L27/10 ,  H01L45/04 ,  H03H7/0153 ,  H03H7/06

Abstract: Many kinds of filters are found in electronic circuits and provide a range of signal processing applications. Such filters can be passive, active, analogue or digital and work across a range of frequencies. Present techniques provide an electronic filter circuit comprising resistive and capacitive elements, wherein a resistive element of the filter circuit is provided by a correlated electron material device.

公开(公告)号：US20180150389A1

公开(公告)日：2018-05-31

申请号：US15361804

申请日：2016-11-28

Applicant: ARM Limited

Inventor： Mudit BHARGAVA ,  Joel Thornton IRBY ,  Vikas CHANDRA

IPC: G06F12/02 ,  H04L9/32

Abstract: A method and apparatus is provided for wear leveling of a storage medium in an electronic device. Wear leveling is achieved by mapping each logical memory address to a corresponding physical memory address. The mapping information is consistent over an on-period of a power cycle, but changes from one power cycle to another. The mapping information, such as a key value for example, may be stored in non-volatile memory such as, for example, a correlated electron random switch (CES) storage element. The mapping may be obtained by manipulating bits of the logical address to obtain the physical address.