公开(公告)号：US20160126939A1

公开(公告)日：2016-05-05

申请号：US14531419

申请日：2014-11-03

Applicant: ARM LIMITED

Inventor： Satheesh BALASUBRAMANIAN ,  James Dennis DODRILL

IPC: H03K3/3562

CPC classification number: H03K3/35625 ,  H03K3/0372

Abstract: A synchroniser flip-flop is provided, which is able to better respond to input values that are not provided for the necessary setup or hold times. The flip-flop includes a latch that includes inverter circuitry for producing a first signal and a signal in dependence on a value of an input signal at a node. A clocked inverter includes a first switch that is connected between a first reference voltage supply and an intermediate node and a second switch, which is connected between the intermediate node and a second reference voltage supply. The first switch is controlled by the first signal and the second switch is controlled by the second signal to produce an output signal at the intermediate node.

Abstract translation: 提供了同步器触发器，其能够更好地响应不为必要的建立或保持时间提供的输入值。 触发器包括锁存器，其包括用于根据节点处的输入信号的值产生第一信号和信号的反相器电路。 时钟反相器包括连接在第一参考电压源和中间节点之间的第一开关和连接在中间节点和第二参考电压源之间的第二开关。 第一开关由第一信号控制，第二开关由第二信号控制，以在中间节点产生输出信号。

公开(公告)号：US20170185709A1

公开(公告)日：2017-06-29

申请号：US15456634

申请日：2017-03-13

Applicant: ARM Limited

Inventor： Marlin Wayne FREDERICK, JR. ,  Karen Lee DELK ,  Lena AHLEN ,  James Dennis DODRILL

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5081 ,  G06F2217/84

Abstract: A static timing analysis method and apparatus that determine an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.

公开(公告)号：US20210133027A1

公开(公告)日：2021-05-06

申请号：US16669906

申请日：2019-10-31

Applicant: Arm Limited

Inventor： Joel Thornton IRBY ,  Wendy Arnott ELSASSER ,  Mudit BHARGAVA ,  Yew Keong CHONG ,  George McNeil LATTIMORE ,  James Dennis DODRILL

IPC: G06F11/10 ,  G06N20/00 ,  G11C7/10 ,  G11C5/14

Abstract: A system-on-chip is provided that includes functional circuitry that performs a function. Control circuitry controls the function based one or more configuration parameters. Non-volatile storage circuitry includes a plurality of non-volatile storage cells each being adapted to write at least a bit of the one or more configuration parameters in a rewritable, persistent manner a plurality of times. Read circuitry locally accesses the non-volatile storage circuitry, obtains the one or more configuration parameters from the non-volatile storage circuitry and provides the one or more configuration parameters to the control circuitry. Write circuitry obtains the one or more configuration parameters and provides the one or more configuration parameters to the non-volatile storage circuitry by locally accessing the non-volatile storage circuitry.

公开(公告)号：US20160357894A1

公开(公告)日：2016-12-08

申请号：US15239991

申请日：2016-08-18

Applicant: ARM LIMITED

Inventor： Marlin Wayne FREDERICK, JR. ,  Karen Lee DELK ,  Lena AHLEN ,  James Dennis DODRILL

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5081 ,  G06F2217/84

Abstract: A static timing analysis method that determines an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.