公开(公告)号：US20210011638A1

公开(公告)日：2021-01-14

申请号：US16507348

申请日：2019-07-10

申请人： Arm Limited

发明人： Christopher Neal HINDS ,  Jesse Garrett BEU ,  Alejandro RICO CARRO ,  Jose Alberto JOAO

IPC分类号： G06F3/06 ,  G06F9/30

摘要： Non-volatile storage circuitry is provided as primary storage accessible to processing circuitry, e.g. as registers, a cache, scratchpad memory, TLB or on-chip RAM. Power control circuitry powers down a given region of the non-volatile storage circuitry when information stored in said given region is not being used. This provides opportunities for more frequent power savings than would be possible if primary storage was implemented using volatile storage.

公开(公告)号：US20200142826A1

公开(公告)日：2020-05-07

申请号：US16182741

申请日：2018-11-07

申请人： Arm Limited

发明人： Joshua RANDALL ,  Alejandro Rico CARRO ,  Jose Alberto JOAO ,  Richard William EARNSHAW ,  Alasdair GRANT

IPC分类号： G06F12/0802

摘要： Aspects of the present disclosure relate to an apparatus comprising a requester master processing device having an associated private cache storage to store data for access by the requester master processing device. The requester master processing device is arranged to issue a request to modify data that is associated with a given memory address and stored in a private cache storage associated with a recipient master processing device. The private cache storage associated with the recipient master processing device is arranged to store data for access by the recipient master processing device. The apparatus further comprises the recipient master processing device having its private cache storage. One of the recipient master processing device and its associated private cache storage is arranged to perform the requested modification of the data while the data is stored in the cache storage associated with the recipient master processing device.

公开(公告)号：US20220035679A1

公开(公告)日：2022-02-03

申请号：US16943117

申请日：2020-07-30

申请人： Arm Limited

发明人： Dam SUNWOO ,  Supreet JELOKA ,  Saurabh Pijuskumar SINHA ,  Jaekyu LEE ,  Jose Alberto JOAO ,  Krishnendra NATHELLA

IPC分类号： G06F9/50 ,  G06N20/00 ,  G06N5/04

摘要： A method for controlling hardware resource configuration for a processing system comprises obtaining performance monitoring data indicative of processing performance associated with workloads to be executed on the processing system, providing a trained machine learning model with input data depending on the performance monitoring data; and based on an inference made from the input data by the trained machine learning model, setting control information for configuring the processing system to control an amount of hardware resource allocated for use by at least one processor core. A corresponding method of training the model is provided. This is particularly useful for controlling inter-core borrowing of resource between processor cores in a multi-core processing system, where resource is borrowed between respective cores, e.g. cores on different layers of a 3D integrated circuit.

公开(公告)号：US20180276046A1

公开(公告)日：2018-09-27

申请号：US15464574

申请日：2017-03-21

申请人： ARM Limited

发明人： Jose Alberto JOAO ,  Alejandro Rico CARRO ,  Ziqiang HUANG

IPC分类号： G06F9/50 ,  G06F9/48 ,  G06F9/52 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/084

CPC分类号： G06F9/5044 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/3802 ,  G06F9/3855 ,  G06F9/4881 ,  G06F9/52 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/452 ,  G06F2212/62

摘要： An apparatus has processing circuitry to execute instructions from multiple threads and hardware registers to store context data for the multiple threads concurrently. At a given time a certain number of software-scheduled threads may be scheduled for execution by software executed by the processing circuitry. Hardware thread scheduling circuitry is provided to select one or more active threads to be executed from among the software-scheduled threads. The hardware thread scheduling circuitry adjusts the number of active threads in dependence on at least one performance metric indicating performance of the threads.

公开(公告)号：US20180253299A1

公开(公告)日：2018-09-06

申请号：US15450430

申请日：2017-03-06

申请人： ARM Limited

发明人： Jose Alberto JOAO ,  Ziqiang HUANG ,  Alejandro Rico CARRO

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3009 ,  G06F9/3005 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867 ,  G06F9/4881

摘要： An apparatus comprises processing circuitry for executing instructions of two or more threads of processing, hardware registers to store context data for the two or more threads concurrently, and commit circuitry to commit results of executed instructions of the threads, where for each thread the commit circuitry commits the instructions of that thread in program order. At least one defer buffer is provided to buffer at least one blocked instruction for which execution by the processing circuitry is complete but execution of an earlier instruction of the same thread in the program order is incomplete. This can help to resolve inter-thread blocking and hence improve performance.