公开(公告)号：US09697908B1

公开(公告)日：2017-07-04

申请号：US15179686

申请日：2016-06-10

Applicant: ARM Limited

Inventor： Kapil Rathi ,  Abhishek Kumar Shrivastava ,  Vikash

IPC: G11C17/00 ,  G11C17/08 ,  G11C13/00 ,  G11C17/12 ,  G11C17/10

CPC classification number: G11C17/08 ,  G11C13/0007 ,  G11C17/10 ,  G11C17/12 ,  G11C17/123

Abstract: Various implementations described herein may refer to and may be directed to non-discharging read-only memory cells. For instance, in one implementation, an integrated circuit may include a read-only memory (ROM) array including a plurality of ROM cells arranged into a column, where the column is disposed proximate to a bit line and to a reference voltage line. The plurality of ROM cells arranged into the column may include a plurality of non-discharging ROM cells positioned adjacently to one another, where each non-discharging ROM cell has a source terminal, a drain terminal, or both coupled to at least one adjacent non-discharging ROM cell. In addition, the plurality of non-discharging ROM cells may be coupled to the bit line using two or fewer connections.