公开(公告)号：US20240354216A1

公开(公告)日：2024-10-24

申请号：US18577972

申请日：2022-06-10

Applicant: Arm Limited

Inventor： Matthew Lucien Evans ,  Robert Gwilym Dimond ,  Alexander Donald Charles Chadwick

IPC: G06F11/34 ,  G06F12/1009 ,  G06F12/1027

CPC classification number: G06F11/3471 ,  G06F12/1009 ,  G06F12/1027

Abstract: An apparatus comprises: memory access circuitry (11) to process memory access requests requesting access to a memory system (10, 32); and access frequency tracking circuitry (40). In response to a given memory access request requesting access to a given page of a memory address space, the access frequency tracking circuitry (40) determines an outcome of a chance-dependent test, where the outcome of the chance-dependent test is dependent on chance. When the outcome of the chance-dependent test is a first outcome, an access frequency tracking indicator corresponding to the given page is updated within an access frequency tracking structure. When the chance-dependent test has an outcome other than the first outcome. the access frequency tracking circuitry 40 omits updating of the access frequency tracking indicator corresponding to the given page.

公开(公告)号：US11467960B1

公开(公告)日：2022-10-11

申请号：US17377873

申请日：2021-07-16

Applicant: Arm Limited

Inventor： Robert Gwilym Dimond ,  Matthew Lucien Evans

IPC: G06F12/08 ,  G06F12/0802

Abstract: An access frequency caching hardware structure has entries each storing an access frequency counter indicative of a frequency of accesses to a corresponding page of a memory address space. Access frequency tracking circuitry is responsive to a given memory access request requesting access to a target page, to determine whether the access frequency caching hardware structure already includes a corresponding entry which is valid and corresponds to the target page. When the structure includes the corresponding entry, a corresponding access frequency counter specified by the corresponding entry is incremented. In response to a counter writeback event associated with a selected access frequency counter corresponding to a selected page, an update is made to a global access frequency counter corresponding to the selected page within a global access frequency tracking data structure stored in the memory system.

公开(公告)号：US11194485B2

公开(公告)日：2021-12-07

申请号：US16624039

申请日：2018-06-08

Applicant: ARM LIMITED

Inventor： Jason Parker ,  Matthew Lucien Evans ,  Gareth Rhys Stockwell ,  Djordje Kovacevic

IPC: G06F3/06 ,  G06F12/0804

Abstract: Memory access circuitry enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry 8. In response to a realm switch from a source realm to a target realm at a more privileged exception level, state masking of a subset of architectural state associated with a source realm is performed to make the state inaccessible to a target realm. In response to a flush command following the realm switch, any of the subset of architectural state data not already saved to at least one realm execution context memory region is ensured to be saved.

公开(公告)号：US11119943B2

公开(公告)日：2021-09-14

申请号：US15019069

申请日：2016-02-09

Applicant: ARM LIMITED

Inventor： Matthew Lucien Evans

IPC: G06F12/1036

Abstract: A memory management unit comprises an interface for receiving an address translation request from a device, the address translation request specifying a virtual request to be translated. Translation circuitry translates the virtual address into an intermediate address different from a physical address directly specifying a memory location. The interface provides an address translation response specifying the intermediate address to the device in response to the address translation request. This improves security by avoiding exposure of physical addresses to the device.

公开(公告)号：US10558590B2

公开(公告)日：2020-02-11

申请号：US15574938

申请日：2016-04-26

Applicant: ARM LIMITED

Inventor： Jason Parker ,  Richard Roy Grisenthwaite ,  Andrew Christopher Rose ,  Matthew Lucien Evans

IPC: G06F12/14 ,  G06F12/06

Abstract: A data processing system for processing data using a memory having a plurality of memory regions, a given memory region within said plurality of memory regions having an associated owning process having exclusive rights to control access to said given memory region, said system comprising: a security controller to: receive a request to initialise a guest execution environment; claim one or more regions of memory to be owned by said security controller; store executable program code of said guest execution environment within said one or more regions of memory; and transfer ownership of said one or more regions to said guest execution environment.

公开(公告)号：US12197916B2

公开(公告)日：2025-01-14

申请号：US18006813

申请日：2021-07-08

Applicant: ARM LIMITED

Inventor： Nigel John Stephens ,  David Hennah Mansell ,  Richard Roy Grisenthwaite ,  Matthew Lucien Evans ,  Jelena Milanovic

IPC: G06F9/30 ,  G06F9/38

Abstract: Instruction decoder to decode processing instructions; one or more first registers; first processing circuitry to execute the decoded processing instructions in a first processing mode and configured to execute the decoded processing instructions using the one or more first registers; and control circuitry to execute the decoded processing instructions in a second processing mode using one or more second registers; the instruction decoder being configured to decode processing instructions selected from a first instruction set and a second instruction set in the second processing mode, in which one or both of the first and second instruction sets comprises at least one unique instruction set; the instruction decoder configured to decode one or more mode change instructions to change between the first and second processing mode; and the first processing circuitry configured to change the current processing mode between the first and second processing mode responding to executing mode change instruction.

公开(公告)号：US20240211299A1

公开(公告)日：2024-06-27

申请号：US18555041

申请日：2022-03-24

Applicant: Arm Limited

Inventor： Matthew Lucien Evans ,  Robert Gwilym Dimond

IPC: G06F9/455 ,  G06F9/48

CPC classification number: G06F9/45558 ,  G06F9/4856 ,  G06F2009/45579 ,  G06F2009/45583

Abstract: A host device (10) provides a plurality of virtual machines (54) executing one or more processes (60, 62, 64, 66). A peripheral device (30) performs tasks on behalf of the host and is coupled to it via a communication network (20). The peripheral provides a plurality of virtual peripheral devices (34), each allocated to one of the virtual machines. Address translation circuitry (75) in the host performs two-stage address translation. When accessing a memory (40) via the host, the peripheral requests a transfer with a specified address and associated metadata providing a source identifier field, a first address translation control field and a second address translation control field. The first address translation control field controls any first stage address translation and depends on the process. The second address translation control field controls any second stage address translation required and depends on the virtual machine associated with the specified address.

公开(公告)号：US11461248B2

公开(公告)日：2022-10-04

申请号：US16648901

申请日：2018-11-09

Applicant: ARM Limited

Inventor： Jason Parker ,  Martin Weidmann ,  Gareth Rhys Stockwell ,  Matthew Lucien Evans

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/14 ,  G06F21/62 ,  G06F21/78

Abstract: A realm management unit (RMU) manages ownership of memory regions by realms, each realm corresponding to at least a portion of a software process executed by processing circuitry. Memory access circuitry enforces ownership rights for the regions, with the owner realm having a right to exclude other realms from accessing data stored within its owned region. The memory access circuitry permits execution, from within a current realm, of program code stored in a target memory region having an owner realm other than the current realm, when the target memory region is owned by a code realm and a code realm authorisation table 908 stored in at least one memory region owned by the current realm indicates that execution of program code from the target memory region is permitted by the current realm.

公开(公告)号：US11347660B2

公开(公告)日：2022-05-31

申请号：US16623528

申请日：2018-06-11

Applicant: ARM LIMITED

Inventor： Jason Parker ,  Matthew Lucien Evans ,  Gareth Rhys Stockwell ,  Martin Weidmann

IPC: G06F12/00 ,  G06F12/14 ,  G06F9/455

Abstract: Memory access circuitry enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry. A realm management unit initialises the realms. The realm management unit is configured to initialise realms including a full realm which corresponds to a given software process and a sub-realm corresponding to a given address range within the given software process.

公开(公告)号：US11294676B2

公开(公告)日：2022-04-05

申请号：US16625912

申请日：2018-06-08

Applicant: ARM LIMITED

Inventor： Matthew Lucien Evans ,  Jason Parker ,  Gareth Rhys Stockwell ,  Martin Weidmann

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06F11/07

Abstract: Memory access circuitry enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry. In response to a first variant of an exception return instruction the processing circuitry returns from processing of an exception while staying within the same realm. In response to a second variant of the exception return instruction the processing circuitry switches processing from a current realm to a destination realm.