公开(公告)号：US09697136B2

公开(公告)日：2017-07-04

申请号：US14494000

申请日：2014-09-23

Applicant: ARM Limited

Inventor： Ali Ghassan Saidi ,  Anirruddha Nagendran Udipi ,  Matthew Lucien Evans ,  Geoffrey Blake ,  Robert Gwilym Dimond

IPC: G06F12/1027

CPC classification number: G06F12/1027 ,  G06F2212/654 ,  G06F2212/681

Abstract: A data processing system utilizing a descriptor ring to facilitate communication between one or more general purpose processors and one or more devices employs a system memory management unit for managing access by the devices to a main memory. The system memory management unit uses address translation data for translating memory addresses generated by the devices into addresses supplied to the main memory. Prefetching circuitry within the system memory management unit serves to detect pointers read from the descriptor ring and to prefetch address translation data into the translation lookaside buffer of the system memory management unit.

公开(公告)号：US20240354216A1

公开(公告)日：2024-10-24

申请号：US18577972

申请日：2022-06-10

Applicant: Arm Limited

Inventor： Matthew Lucien Evans ,  Robert Gwilym Dimond ,  Alexander Donald Charles Chadwick

IPC: G06F11/34 ,  G06F12/1009 ,  G06F12/1027

CPC classification number: G06F11/3471 ,  G06F12/1009 ,  G06F12/1027

Abstract: An apparatus comprises: memory access circuitry (11) to process memory access requests requesting access to a memory system (10, 32); and access frequency tracking circuitry (40). In response to a given memory access request requesting access to a given page of a memory address space, the access frequency tracking circuitry (40) determines an outcome of a chance-dependent test, where the outcome of the chance-dependent test is dependent on chance. When the outcome of the chance-dependent test is a first outcome, an access frequency tracking indicator corresponding to the given page is updated within an access frequency tracking structure. When the chance-dependent test has an outcome other than the first outcome. the access frequency tracking circuitry 40 omits updating of the access frequency tracking indicator corresponding to the given page.

公开(公告)号：US11467960B1

公开(公告)日：2022-10-11

申请号：US17377873

申请日：2021-07-16

Applicant: Arm Limited

Inventor： Robert Gwilym Dimond ,  Matthew Lucien Evans

IPC: G06F12/08 ,  G06F12/0802

Abstract: An access frequency caching hardware structure has entries each storing an access frequency counter indicative of a frequency of accesses to a corresponding page of a memory address space. Access frequency tracking circuitry is responsive to a given memory access request requesting access to a target page, to determine whether the access frequency caching hardware structure already includes a corresponding entry which is valid and corresponds to the target page. When the structure includes the corresponding entry, a corresponding access frequency counter specified by the corresponding entry is incremented. In response to a counter writeback event associated with a selected access frequency counter corresponding to a selected page, an update is made to a global access frequency counter corresponding to the selected page within a global access frequency tracking data structure stored in the memory system.

公开(公告)号：US09977679B2

公开(公告)日：2018-05-22

申请号：US14935820

申请日：2015-11-09

Applicant: ARM Limited

Inventor： Ian Michael Caulfield ,  Antony John Penton ,  Robert Gwilym Dimond

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3867 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/3009 ,  G06F9/3802 ,  G06F9/3851 ,  G06F9/3861

Abstract: An apparatus and method are provided for processing instructions from a plurality of threads. The apparatus comprises a processing pipeline to process instructions, including fetch circuitry to fetch instructions from a plurality of threads for processing by the processing pipeline, and execution circuitry to execute the fetched instructions. Execution hint instruction handling circuitry is then responsive to the fetch circuitry fetching an execution hint instruction for a first thread, to treat the execution hint instruction, at least in a presence of a suspension condition, as a predicted branch instruction with a predicted behavior, and to cause the fetch circuitry to suspend fetching of instructions for the first thread. The execution circuitry is then arranged to execute the predicted branch instruction with a behavior different to the predicted behavior, in order to trigger a misprediction condition. The fetch circuitry is then responsive to the misprediction condition to resume fetching of instructions for the first thread. This provides a reliable mechanism for temporarily suspending fetching of instructions for a thread in response to a hint instruction, whilst still reliably resuming fetching in due course.

公开(公告)号：US20240211299A1

公开(公告)日：2024-06-27

申请号：US18555041

申请日：2022-03-24

Applicant: Arm Limited

Inventor： Matthew Lucien Evans ,  Robert Gwilym Dimond

IPC: G06F9/455 ,  G06F9/48

CPC classification number: G06F9/45558 ,  G06F9/4856 ,  G06F2009/45579 ,  G06F2009/45583

Abstract: A host device (10) provides a plurality of virtual machines (54) executing one or more processes (60, 62, 64, 66). A peripheral device (30) performs tasks on behalf of the host and is coupled to it via a communication network (20). The peripheral provides a plurality of virtual peripheral devices (34), each allocated to one of the virtual machines. Address translation circuitry (75) in the host performs two-stage address translation. When accessing a memory (40) via the host, the peripheral requests a transfer with a specified address and associated metadata providing a source identifier field, a first address translation control field and a second address translation control field. The first address translation control field controls any first stage address translation and depends on the process. The second address translation control field controls any second stage address translation required and depends on the virtual machine associated with the specified address.

公开(公告)号：US11106513B2

公开(公告)日：2021-08-31

申请号：US16755269

申请日：2018-09-04

Applicant: ARM Limited

Inventor： Robert Gwilym Dimond ,  Eric Biscondi ,  Mario Torrecillas Rodriguez ,  Paul Stanley Hughes

IPC: G06F9/44 ,  G06F9/54 ,  G06F9/30 ,  G06F12/02 ,  G06F12/0873

Abstract: A data processing system and method of data processing are provided. The system comprises first and second data processing agents and data storage shared coherently between the both data processing agents to store a message data structure to provide a message channel between them. A further data storage is accessible to both data processing agents to store message channel metadata, which provides message status information for the message channel. The message channel metadata is one of a plurality of message channel metadata types defined for a corresponding plurality of message channel types between the first and second data processing agents, and at least one of the first and second data processing agents is responsive to an initialization trigger to establish the message channel with a selected message channel type.