公开(公告)号：US09582282B2

公开(公告)日：2017-02-28

申请号：US14333889

申请日：2014-07-17

Applicant: ARM Limited

Inventor： Mitchell Bryan Hayenga ,  Christopher Daniel Emmons

IPC: G06F9/38 ,  G06F12/0862 ,  G06F12/08

CPC classification number: G06F9/3816 ,  G06F9/3802 ,  G06F12/0862 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/452 ,  G06F2212/6024

Abstract: A data processing apparatus has prefetch circuitry for prefetching cache lines of instructions into an instruction cache. A prefetch lookup table is provided for storing prefetch entries, with each entry corresponding to a region of a memory address space and identifying at least one block of one or more cache lines within the corresponding region from which processing circuitry accessed an instruction on a previous occasion. When the processing circuitry executes an instruction from a new region, the prefetch circuitry looks up the table, and if it stores a prefetch entry for the new region, then the at least one block identified by the corresponding entry is prefetched into the cache.

Abstract translation: 数据处理装置具有用于将高速缓存行指令预取到指令高速缓存中的预取电路。 提供预取查找表用于存储预取条目，其中每个条目对应于存储器地址空间的区域，并且识别处理电路在其中访问了先前场合的指令的相应区域内的一个或多个高速缓存行的至少一个块 。 当处理电路执行来自新区域的指令时，预取电路查找该表，并且如果它存储新区域的预取条目，则由相应条目标识的至少一个块被预取到高速缓存中。

公开(公告)号：US10725992B2

公开(公告)日：2020-07-28

申请号：US16207241

申请日：2018-12-03

Applicant: ARM LIMITED

Inventor： Mitchell Bryan Hayenga ,  Curtis Glenn Dunham ,  Dam Sunwoo

IPC: G06F16/22 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1027 ,  G06F9/38 ,  G06F16/172 ,  G06F21/75

Abstract: An apparatus has processing circuitry for processing instructions from multiple threads. A storage structure is shared between the threads and has a number of entries. Indexing circuitry generates a target index value identifying an entry of the storage structure to be accessed in response to a request from the processing circuitry specifying a requested index value corresponding to information to be accessed from the storage structure. The indexing circuitry generates the target index value as a function of the requested index value and a key value selected depending on which of the threads trigger the request. The key value for at least one of the threads is updated from time to time.

公开(公告)号：US10324727B2

公开(公告)日：2019-06-18

申请号：US15238778

申请日：2016-08-17

Applicant: ARM LIMITED

Inventor： Curtis Glenn Dunham ,  Mitchell Bryan Hayenga

IPC: G06F9/38 ,  G06F9/30

Abstract: A data processing apparatus executes a stream of instructions. Memory access circuitry accesses a memory in response to control signals associated with a memory access instruction that is executed in the stream of instructions. Branch prediction circuitry predicts the outcome of branch instructions in the stream of instructions based on a branch prediction table. Processing circuitry performs a determination of whether out-of-order execution of memory access instructions is to be performed based on memory prediction data, and selectively enables out-of-order execution of the memory access instructions in dependence on the determination. The memory prediction data is stored in the branch prediction table.

公开(公告)号：US10185731B2

公开(公告)日：2019-01-22

申请号：US15086866

申请日：2016-03-31

Applicant: ARM LIMITED

Inventor： Mitchell Bryan Hayenga ,  Curtis Glenn Dunham ,  Dam Sunwoo

IPC: G06F17/30 ,  G06F12/0875

Abstract: An apparatus has processing circuitry for processing instructions from multiple threads. A storage structure is shared between the threads and has a number of entries. Indexing circuitry generates a target index value identifying an entry of the storage structure to be accessed in response to a request from the processing circuitry specifying a requested index value corresponding to information to be accessed from the storage structure. The indexing circuitry generates the target index value as a function of the requested index value and a key value selected depending on which of the threads trigger the request. The key value for at least one of the threads is updated from time to time.