公开(公告)号：US20240020419A1

公开(公告)日：2024-01-18

申请号：US17812834

申请日：2022-07-15

Applicant: Arm Limited

Inventor： Matthew David HADDON ,  Igor FEDOROV ,  Reiley JEYAPAUL ,  Paul Nicholas WHATMOUGH ,  Zhi-Gang LIU

IPC: G06F21/64 ,  G06F16/23 ,  G06F16/22

CPC classification number: G06F21/64 ,  G06F16/2365 ,  G06F16/2264

Abstract: Methods and systems for detecting errors when performing a convolutional operation is provided. Predicted checksum data, corresponding to input checksum data and kernel checksum data, is obtained. The convolutional operation is performed to obtain an output feature map. Output checksum data is generated and the predicted checksum data and the output checksum data are compared, the comparing taking account of partial predicted checksum data configured to correct for a lack of padding when performing the convolution operation, wherein the partial predicted checksum data corresponds to input checksum data for a subset of the values in the input feature map and kernel checksum data for a subset of the values in the kernel.

公开(公告)号：US20200034230A1

公开(公告)日：2020-01-30

申请号：US16043975

申请日：2018-07-24

Applicant: Arm Limited

Inventor： Reiley JEYAPAUL ,  Roxana RUSITORU ,  Jonathan Curtis BEARD

IPC: G06F11/10 ,  G06F11/20 ,  G06F11/00 ,  G11C29/00 ,  G06F12/02 ,  G06F3/06

Abstract: A memory system for a data processing apparatus includes a fault management unit, a memory controller (such as a memory management unit or memory node controller), and one or more storage devices accessible via the memory controller and configured for storing critical data. The fault management unit detects and corrects a fault in the stored critical data, a storage device or the memory controller. A data fault may be corrected using a copy of the data, or an error correction code, for example. A level of failure protection for the critical data, such as a number of copies, an error correction code or a storage location in the one or more storage devices, is determined dependent upon a failure characteristic of the device. A failure characteristic, such as an error rate, may be monitored and updated dynamically.

公开(公告)号：US20200174072A1

公开(公告)日：2020-06-04

申请号：US16512911

申请日：2019-07-16

Applicant: Arm Limited

Inventor： Balaji VENU ,  Reiley JEYAPAUL

IPC: G01R31/317

Abstract: An apparatus is provided to measure vulnerability of a circuit to transient errors. The circuit includes processing circuitry and a plurality of flops. The apparatus includes categorisation obtaining circuitry that obtains a vulnerability categorisation of the flops. The vulnerability categorisation indicates whether each flop is vulnerable, conditionally vulnerable, or isolated. Analysis circuitry determines, for at least one cycle of the processing circuitry, a set of the flops that are currently vulnerable, based on the vulnerability categorisation of the flops.

公开(公告)号：US20190121689A1

公开(公告)日：2019-04-25

申请号：US16225523

申请日：2018-12-19

Applicant: ARM Limited

Inventor： Reiley JEYAPAUL ,  Balaji VENU ,  Xabier ITURBE ,  Emre ÖZER ,  Antony John PENTON

IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06

Abstract: Aspects of the present disclosure relate to an apparatus comprising processing circuitry to execute a plurality of code sequences, and configuration storage to store mode control data for the processing circuitry. When the processing circuitry is executing one of said plurality of code sequences, the mode control data is set so as to identify a high resilience mode of operation of the processing circuitry where usage of one or more components of the processing circuitry is modified so as to increase resilience of the processing circuitry to faults relative to a default mode of operation of the processing circuitry.

公开(公告)号：US20230367676A1

公开(公告)日：2023-11-16

申请号：US17742875

申请日：2022-05-12

Applicant: Arm Limited

Inventor： Reiley JEYAPAUL ,  Roxana RUSITORU ,  Jonathan Curtis BEARD ,  Kar-Lik Kasim WONG

IPC: G06F11/14 ,  G06F8/41

CPC classification number: G06F11/1407 ,  G06F8/433

Abstract: An apparatus comprises at least one processor to execute software processes, a memory system to store data for access by the at least one processor, and checkpointing circuitry to trigger saving, to the memory system, of checkpoints of context state associated with at least one software process executed by the at least one processor. The saving of checkpoints is a background process performed by the checkpointing circuitry in the background of execution of the software processes by the at least one processor.

公开(公告)号：US20200174863A1

公开(公告)日：2020-06-04

申请号：US16206189

申请日：2018-11-30

Applicant: Arm Limited

Inventor： Reiley JEYAPAUL ,  Balaji VENU

IPC: G06F11/00 ,  G06F17/50

Abstract: An apparatus is provided to measure vulnerability of a circuit to transient errors. The circuit includes processing circuitry and a plurality of flops. The apparatus includes categorisation obtaining circuitry that obtains a vulnerability categorisation of the flops. The vulnerability categorisation indicates whether each flop is vulnerable, conditionally vulnerable, or isolated. Analysis circuitry determines, for one cycle of the processing circuitry, a set of the flops that are currently vulnerable, based on the vulnerability categorisation of the flops.