-
公开(公告)号：US20240086201A1
公开(公告)日：2024-03-14
申请号：US17941404
申请日：2022-09-09
Applicant: Arm Limited
Inventor： Matthew James WALKER , Mbou EYOLE , Giacomo GABRIELLI , Balaji VENU
IPC: G06F9/38
CPC classification number: G06F9/3855 , G06F9/3802
Abstract: One or more triggered-instruction processing elements are provided, a given triggered-instruction processing element comprising execution circuitry to execute processing operations in response to instructions according to a triggered instruction architecture. Input channel processing circuitry receives a given tagged data item (comprising a data value and a tag value) for a given input channel, and in response controls enqueuing of the data value of the given tagged data item to a selected buffer structure selected from among at least two buffer structures mapped onto register storage accessible to one or more of the triggered-instruction processing elements in response to a computation instruction for controlling performance of a computation operation. The selected buffer structure is selected based at least on the tag value, so data values of tagged data items specifying different tag values for the given input channel are allocatable to different buffer structures.
-
公开(公告)号：US20170293541A1
公开(公告)日：2017-10-12
申请号：US15447673
申请日：2017-03-02
Applicant: ARM Limited
Inventor： Balaji VENU , Kauser Yakub JOHAR , Marco BONINO
IPC: G06F11/22 , G06F11/273 , G06F11/27
CPC classification number: G06F11/27 , G06F11/0721 , G06F11/0766 , G06F11/0775 , G06F11/0784 , G06F11/22 , G06F11/2236 , G06F11/2242 , G06F11/2284 , G06F11/24 , G06F11/273
Abstract: Apparatus and a method for processor core self-testing are disclosed. The apparatus comprises processor core circuitry to perform data processing operations by executing data processing instructions. Separate self-test control circuitry causes the processor core circuitry to temporarily switch from a first state of executing the data processing instructions to a second state of executing a self-test sequence of instructions, before returning to the first state of executing the data processing instructions without a reboot of the processor core circuitry being required. There is also self-test support circuitry, wherein the processor core circuitry is responsive to the self-test sequence of instructions to cause an export of at least one self-test data item via the self-test support circuitry to the self-test control circuitry.
-
公开(公告)号：US20240086196A1
公开(公告)日：2024-03-14
申请号：US17941387
申请日：2022-09-09
Applicant: Arm Limited
Inventor： Matthew James WALKER , Mbou EYOLE , Giacomo GABRIELLI , Balaji VENU
CPC classification number: G06F9/30123 , G06F9/4881
Abstract: There is provided an apparatus, method and medium for data processing. The apparatus comprises a register file comprising a plurality of data registers, and frontend circuitry responsive to an issued instruction, to control processing circuitry to perform a processing operation to process an input data item to generate an output data item. The processing circuitry is responsive to a first encoding of the issued instruction specifying a data register, to read the input data item from the data register, and/or write the output data item to the data register. The processing circuitry is responsive to a second encoding of the issued instruction specifying a buffer-region of the register file for storing a queue of data items, to perform the processing operation and to perform a dequeue operation to dequeue the input data item from the queue, and/or perform an enqueue operation to enqueue the output data item to the queue.
-
公开(公告)号：US20180307430A1
公开(公告)日：2018-10-25
申请号：US15493609
申请日：2017-04-21
Applicant: ARM Limited
Inventor： Xabier ITURBE , Emre ÖZER , Balaji VENU , Antony John PENTON
CPC classification number: G06F3/0634 , G06F3/0604 , G06F3/0619 , G06F3/0673 , G06F11/1076
Abstract: An apparatus and method are provided for increasing resilience to faults. The apparatus comprises processing circuitry for executing a plurality of code sequences including at least one critical code sequence, and configuration storage for storing mode control data for the processing circuitry. When the processing circuitry is executing a critical code sequence, the mode control data is set so as to identify a high resilience mode of operation of the processing circuitry, where usage of one or more components of the processing circuitry is modified so as to increase resilience of the processing circuitry to faults relative to a default mode of operation of the processing circuitry. By increasing the resilience to faults, this reduces the chance that any such fault will manifest itself as an error in the processing operations being performed by the apparatus.
-
公开(公告)号：US20240028337A1
公开(公告)日：2024-01-25
申请号：US18247595
申请日：2021-08-17
Applicant: ARM LIMITED
Inventor： Jacob EAPEN , Matthias Lothar BOETTCHER , Balaji VENU , François Christopher Jacques BOTMAN
IPC: G06F9/30
CPC classification number: G06F9/30145 , G06F9/30021 , G06F9/30038
Abstract: A masked-vector-comparison instruction specifies a source vector operand comprising a plurality of source data elements, a mask value, and a comparison target operand. In response to the masked-vector-comparison instruction, an instruction decoder 10 controls processing circuitry 16 to: for each active source data element of the source vector operand, determine whether the active source data element satisfies a comparison condition, based on a masked comparison between one or more compared bits of the active source data element and one or more compared bits of the comparison target operand, the mask value specifying a pattern of compared bits and non-compared bits within the comparison target operand and the active source data element; and generate a result value indicative of which of the source data elements of the source vector operand, if any, is an active source data element satisfying the comparison condition. This instruction is useful for variable length decoding operations.
-
Patent Agency Ranking
6.发明申请公开(公告)号：US20190012242A1
公开(公告)日：2019-01-10
申请号：US15645053
申请日：2017-07-10
Applicant: ARM LIMITED
Inventor： Emre ÖZER , Balaji VENU , Xabier ITURBE , Antony John PENTON
IPC: G06F11/16
Abstract: An apparatus and method are provided for checking output data during redundant execution of instructions. The apparatus has first processing circuitry for executing a sequence of instructions and second processing circuitry for redundantly executing the sequence of instructions. Error code generation circuitry is used to generate an error code from the first output data generated by the first processing circuitry. Error checking circuitry then uses that error code to perform an error checking operation on redundant output data from the second processing circuitry. As a result of the error checking operation, the error checking circuitry then generates a comparison indication signal to indicate that the first output data differs from the redundant output data when the error checking operation detects an error. This provides a very efficient mechanism for implicitly comparing the output data from the first processing circuitry and the second processing circuitry during redundant execution.
-
公开(公告)号：US20180129573A1
公开(公告)日：2018-05-10
申请号：US15800145
申请日：2017-11-01
Applicant: ARM Limited
Inventor： Xabier ITURBE , Emre OZER , Balaji VENU
CPC classification number: G06F11/1608 , G06F11/0793 , G06F11/1008 , G06F11/1645 , G06F11/1658 , G06F11/184 , G06F11/187
Abstract: An apparatus 2 comprises at least three processing circuits 4 to perform redundant processing of a common thread of program instructions. Error detection circuitry 16 is provided comprising a number of comparators 22 for detecting a mismatch between signals on corresponding signal nodes 20 in the processing circuits 4. When a comparator 22 detects a mismatch, this triggers a recovery process. The error detection circuitry 16 generates an unresolvable error signal 36 indicating that a detected area is unresolvable by the recovery process when, during the recovery process, a mismatch is detected by one of the proper subset 34 of the comparators 22. By considering fewer comparators 22 during the recovery process than during normal operation, the chances of unrecoverable errors being detected can be reduced, increasing system availability.
-
公开(公告)号：US20200174072A1
公开(公告)日：2020-06-04
申请号：US16512911
申请日：2019-07-16
Applicant: Arm Limited
Inventor： Balaji VENU , Reiley JEYAPAUL
IPC: G01R31/317
Abstract: An apparatus is provided to measure vulnerability of a circuit to transient errors. The circuit includes processing circuitry and a plurality of flops. The apparatus includes categorisation obtaining circuitry that obtains a vulnerability categorisation of the flops. The vulnerability categorisation indicates whether each flop is vulnerable, conditionally vulnerable, or isolated. Analysis circuitry determines, for at least one cycle of the processing circuitry, a set of the flops that are currently vulnerable, based on the vulnerability categorisation of the flops.
-
公开(公告)号：US20190121689A1
公开(公告)日：2019-04-25
申请号：US16225523
申请日：2018-12-19
Applicant: ARM Limited
Inventor： Reiley JEYAPAUL , Balaji VENU , Xabier ITURBE , Emre ÖZER , Antony John PENTON
Abstract: Aspects of the present disclosure relate to an apparatus comprising processing circuitry to execute a plurality of code sequences, and configuration storage to store mode control data for the processing circuitry. When the processing circuitry is executing one of said plurality of code sequences, the mode control data is set so as to identify a high resilience mode of operation of the processing circuitry where usage of one or more components of the processing circuitry is modified so as to increase resilience of the processing circuitry to faults relative to a default mode of operation of the processing circuitry.
-
公开(公告)号：US20180267866A1
公开(公告)日：2018-09-20
申请号：US15463066
申请日：2017-03-20
Applicant: ARM Limited
Inventor： Balaji VENU , Xabier ITURBE , Emre ÖZER
CPC classification number: G06F11/1641 , G06F11/1629 , G06F11/184
Abstract: An apparatus comprises at least three processing circuits to perform redundant processing of common program instructions. Error detection circuitry coupled to a plurality of signal nodes of each of said at least three processing circuits comprises comparison circuitry to detect a mismatch between signals on corresponding signal nodes in said at least three processing circuits, the plurality of signal nodes forming a first group of signal nodes and a second group of signal nodes. In response to the mismatch being detected in relation to corresponding signal nodes within the first group, the error detection circuitry is configured to generate a first trigger for a full recovery process for resolving an error detected for an erroneous processing circuit using state information derived from at least two other processing circuits. In response to the mismatch being detected in relation to corresponding signal nodes within the second group the error detection circuitry is configured to generate a second trigger for a targeted recovery process for a subset of components of the erroneous processing circuit. By implementing a targeted recovery process for a subset of components of an erroneous processing circuit a cheaper recovery process may be provided.
-
-
-
-
-
-
-
-
-
Search Results
16
records
(took 0.024 seconds)
