公开(公告)号：US20220327009A1

公开(公告)日：2022-10-13

申请号：US17225674

申请日：2021-04-08

Applicant: Arm Limited

Inventor： Jonathan Curtis BEARD ,  Curtis Glenn DUNHAM ,  Andreas Lars SANDBERG ,  Roxana RUSITORU

IPC: G06F9/54 ,  G06F15/78 ,  G06F12/1009 ,  G06F12/02

Abstract: Message passing circuitry comprises lookup circuitry responsive to a producer request indicating message data provided on a target message channel by a producer node of a system-on-chip, to obtain, from a channel consumer information structure, selected channel consumer information associated with a given consumer node subscribing to the target message channel. Control circuitry writes the message data to a location associated with an address in a consumer-defined region of address space determined based on the selected channel consumer information. When an event notification condition is satisfied for the target message channel and the given consumer node, and an event notification channel is to be used, event notification data is written to a location associated with an address in a consumer-defined region of address space determined based on event notification channel consumer information associated with the event notification channel.

公开(公告)号：US20170344480A1

公开(公告)日：2017-11-30

申请号：US15166458

申请日：2016-05-27

Applicant: ARM Limited

Inventor： Jonathan Curtis BEARD ,  Wendy ELSASSER ,  Stephan DIESTELHORST

IPC: G06F12/0831 ,  G06F12/0811 ,  G06F12/084

Abstract: A data processing apparatus includes one or more host processors with first processing units, one or more caches with second processing unit, a non-cache memory having a third processing unit and a reorder buffer operable to maintain data order during execution of a program of instructions. An instruction scheduler routes instructions to the processing units. Data coherence is maintained by control logic that blocks access to data locations in use by a selected processing unit other than the selected processing unit until data associated with the data locations are released from the reorder buffer. Data stored in the cache is written to the memory if it is already in a modified state, otherwise the state is set to the modified state. A memory controller may be used to restrict access to memory locations to be operated on.

公开(公告)号：US20230102006A1

公开(公告)日：2023-03-30

申请号：US17484155

申请日：2021-09-24

Applicant: Arm Limited

Inventor： Jonathan Curtis BEARD ,  Luis Emilio PENA

IPC: G06F12/1045 ,  G06F12/1072

Abstract: A hinter data processing apparatus is provided with processing circuitry that determines that an execution context to be executed on a hintee data processing apparatus will require a virtual-to-physical address translation. Hint circuitry transmits a hint to a hintee data processing apparatus to prefetch a virtual-to-physical address translation in respect of an execution context of the further data processing apparatus. A hintee data processing apparatus is also provided with receiving circuitry that receives a hint from a hinter data processing apparatus to prefetch a virtual-to-physical address translation in respect of an execution context of the further data processing apparatus. Processing circuitry determines whether to follow the hint and, in response to determining that the hint is to be followed, causes the virtual-to-physical address translation to be prefetched for the execution context of the data processing apparatus. In both cases, the hint comprises an identifier of the execution context.

公开(公告)号：US20190102272A1

公开(公告)日：2019-04-04

申请号：US15724433

申请日：2017-10-04

Applicant: ARM LIMITED

Inventor： Prakash S. RAMRAKHYANI ,  Jonathan Curtis BEARD

IPC: G06F11/30

CPC classification number: G06F11/3024 ,  G06F11/3037 ,  G06F2201/885 ,  G06F2212/1024 ,  G06F12/0802 ,  G06F9/46

Abstract: An apparatus comprises a plurality of memory units organised as a hierarchical memory system, wherein each of at least some of the memory units is associated with a processor element; predictor circuitry to perform a prediction process to determine a predicted redundancy period of result data of a data processing operation to be performed, indicating a predicted point when said result data will be next accessed; and an operation controller to cause a selected processor element to perform said data processing operation, wherein said selected processor element is selected based on said predicted redundancy period.

公开(公告)号：US20190018785A1

公开(公告)日：2019-01-17

申请号：US15819328

申请日：2017-11-21

Applicant: Arm Limited

Inventor： Jonathan Curtis BEARD ,  Roxana RUSITORU ,  Curtis Glenn DUNHAM

IPC: G06F12/1009 ,  G06F12/0802

CPC classification number: G06F12/1009 ,  G06F12/0653 ,  G06F12/0802 ,  G06F12/0862 ,  G06F12/1036 ,  G06F12/1063 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/109 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/154 ,  G06F2212/60 ,  G06F2212/6024 ,  G06F2212/62 ,  G06F2212/651 ,  G06F2212/657

Abstract: A data processing network includes a network of devices addressable via a system address space, the network including a computing device configured to execute an application in a virtual address space. A virtual-to-system address translation circuit is configured to translate a virtual address to a system address. A memory node controller has a first interface to a data resource addressable via a physical address space, a second interface to the computing device, and a system-to-physical address translation circuit, configured to translate a system address in the system address space to a corresponding physical address in the physical address space of the data resource. The virtual-to-system mapping may be a range table buffer configured to retrieve a range table entry comprising an offset address of a range together with a virtual address base and an indicator of the extent of the range.

公开(公告)号：US20180150321A1

公开(公告)日：2018-05-31

申请号：US15361819

申请日：2016-11-28

Applicant: ARM Limited

Inventor： Curtis Glenn DUNHAM ,  Jonathan Curtis BEARD ,  Roxana RUSITORU

IPC: G06F9/48 ,  G06F9/46

CPC classification number: G06F9/4881 ,  G06F9/461 ,  G06F9/4843 ,  G06F12/0831

Abstract: Data processing apparatus comprises a group of two or more processing elements configured to execute processing instructions of a program task; the processing elements being configured to provide context data relating to a program task following execution of that program task by that processing element; and to receive context data, provided by that processing element or another processing element, at resumption of execution of a program task; in which a next processing element of the group to execute a program task is configured to receive a first subset of the context data from a previous processing element to execute that program task and to start to execute the program task using the first subset of the context data; and in which the next processing element is configured to receive one or more items of a second, remaining, subset of the context data during execution of the program task by that processing element.

公开(公告)号：US20250053465A1

公开(公告)日：2025-02-13

申请号：US18446570

申请日：2023-08-09

Applicant: Arm Limited

Inventor： Jonathan Curtis BEARD ,  Steven Douglas KRUEGER

IPC: G06F9/54 ,  G06F15/80

Abstract: A message channel functionality for a data processing system is disclosed. This provides communication channels which may be considered to be a shared resource. The approach combines atomic stores, which are fully completed in a single atomic transaction, and non-coherence to provide non-coherent atomic stores that are conditional to implement primitive communications channels that can be used to implement software queues and channels more efficiently. This enables the programmer to execute a store from registers on one side of a communications link and to have that data appear in the registers of a data consumer on that link directly, bypassing both the shared state upgrade problem and the parallel problem of acquiring a synchronization lock before data send.

公开(公告)号：US20230367676A1

公开(公告)日：2023-11-16

申请号：US17742875

申请日：2022-05-12

Applicant: Arm Limited

Inventor： Reiley JEYAPAUL ,  Roxana RUSITORU ,  Jonathan Curtis BEARD ,  Kar-Lik Kasim WONG

IPC: G06F11/14 ,  G06F8/41

CPC classification number: G06F11/1407 ,  G06F8/433

Abstract: An apparatus comprises at least one processor to execute software processes, a memory system to store data for access by the at least one processor, and checkpointing circuitry to trigger saving, to the memory system, of checkpoints of context state associated with at least one software process executed by the at least one processor. The saving of checkpoints is a background process performed by the checkpointing circuitry in the background of execution of the software processes by the at least one processor.

公开(公告)号：US20180150322A1

公开(公告)日：2018-05-31

申请号：US15361871

申请日：2016-11-28

Applicant: ARM Limited

Inventor： Curtis Glenn DUNHAM ,  Jonathan Curtis BEARD ,  Roxana RUSITORU

IPC: G06F9/48 ,  G06F9/50

Abstract: Data processing apparatus comprises one or more interconnected processing elements each configured to execute processing instructions of a program task; coherent memory circuitry storing one or more copies of data accessible by each of the processing elements, so that data written to a memory address in the coherent memory circuitry by one processing element is consistent with data read from that memory address in the coherent memory circuitry by another of the processing elements; the coherent memory circuitry comprising a memory region to store data, accessible by the processing elements, defining one or more attributes of a program task and context data associated with a most recent instance of execution of that program task; the apparatus comprising scheduling circuitry to schedule execution of a task by a processing element in response to the one or more attributes defined by data stored in the memory region corresponding to that task; and each processing element which executes a program task is configured to modify one or more of the attributes corresponding to that program task in response to execution of that program task.

公开(公告)号：US20220327057A1

公开(公告)日：2022-10-13

申请号：US17225614

申请日：2021-04-08

Applicant: Arm Limited

Inventor： Jonathan Curtis BEARD ,  Jamshed JALAL ,  Steven Douglas KRUEGER ,  Klas Magnus BRUCE

IPC: G06F12/0842 ,  G06F13/40 ,  G06F12/10

Abstract: An apparatus and method for handling stash requests are described. The apparatus has a processing element with an associated storage structure that is used to store data for access by the processing element, and an interface for coupling the processing element to interconnect circuitry. Stash request handling circuitry is also provided that, in response to a stash request targeting the storage structure being received at the interface from the interconnect circuitry, causes a block of data associated with the stash request to be stored within the storage structure. The stash request identifies a given address that needs translating into a corresponding physical address in memory, and also identifies an address space key. Address translation circuitry is used to convert the given address identified by the stash request into the corresponding physical address by performing an address translation that is dependent on the address space key identified by the stash request. The stash request handling circuitry is then responsive to the corresponding physical address determined by the address translation circuitry to cause the block of data to be stored at a location within the storage structure associated with the physical address.