公开(公告)号：US20190221239A1

公开(公告)日：2019-07-18

申请号：US15874444

申请日：2018-01-18

Applicant: Arm Limited

Inventor： Sumant Kumar Thapliyal ,  Sumeet Sawant ,  Avinash Merugu ,  Deeksha Anandani ,  Veera Raghavulu Marella ,  Srinath Gopinath ,  Abdullah Shahid

IPC: G11C5/06 ,  G11C7/18 ,  G11C8/14

CPC classification number: G11C5/06 ,  G11C7/18 ,  G11C8/14 ,  H01L27/0207

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a bitcell and multiple straps including a first strap, a second strap, and a third strap. The first strap may couple the bitcell to ground. The second strap may couple the bitcell to a bitline. The third strap may couple the bitcell to a wordline within a boundary of the bitcell.

公开(公告)号：US10923161B2

公开(公告)日：2021-02-16

申请号：US15874444

申请日：2018-01-18

Applicant: Arm Limited

Inventor： Sumant Kumar Thapliyal ,  Sumeet Sawant ,  Avinash Merugu ,  Deeksha Anandani ,  Veera Raghavulu Marella ,  Srinath Gopinath ,  Abdullah Shahid

IPC: G11C5/06 ,  G11C8/14 ,  G11C7/18 ,  G11C17/12 ,  H01L27/02 ,  H01L27/112

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a bitcell and multiple straps including a first strap, a second strap, and a third strap. The first strap may couple the bitcell to ground. The second strap may couple the bitcell to a bitline. The third strap may couple the bitcell to a wordline within a boundary of the bitcell.

公开(公告)号：US09583209B1

公开(公告)日：2017-02-28

申请号：US14963111

申请日：2015-12-08

Applicant: ARM Limited

Inventor： Rajiv Kumar Roy ,  Fakhruddin Ali Bohra ,  Manish Trivedi ,  Sumant Kumar Thapliyal ,  Vikash

IPC: G11C8/00 ,  G11C17/08

CPC classification number: G11C17/08 ,  G11C8/12

Abstract: Various implementations described herein are directed to an integrated circuit having high density memory architecture. The integrated circuit may include a plurality of bank arrays having multiple segments of bitcells configured to share local control. The integrated circuit may include a plurality of control lines coupling the local control to each of the multiple segments of bitcells. In some instances, during activation of a segment of bitcells by the local control via one of the control lines, another segment of bitcells may be deactivated by the local control via another of the control lines.

Abstract translation: 本文描述的各种实现涉及具有高密度存储器架构的集成电路。 集成电路可以包括具有被配置为共享本地控制的多个位单元段的多个存储体阵列。 集成电路可以包括将本地控制耦合到位单元的多个段中的每一个的多个控制线。 在一些情况下，在本地控制通过控制线之一激活位单元的段时，可以通过另一控制线的本地控制来停用另一段位单元。