公开(公告)号：US20230385127A1

公开(公告)日：2023-11-30

申请号：US17824438

申请日：2022-05-25

Applicant: Arm Limited

Inventor： Timothy HAYES ,  Alejandro Rico CARRO

IPC: G06F9/52 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/52 ,  G06F9/30087 ,  G06F9/3818 ,  G06F9/3802

Abstract: Apparatus comprises a plurality of processing elements; and control circuitry to communicate with the plurality of processing elements by a data communication path; the control circuitry being configured, in response to a request issued by a given processing element of the plurality of processing elements, to initiate a hybrid operation by issuing a command defining the hybrid operation to a group of processing elements comprising at least a subset of the plurality of processing elements, the hybrid operation comprising performance of a control function selected from a predetermined set of one or more control functions and initiation of performance of a synchronization event, the synchronization event comprising each of the group of processing elements providing confirmation that any control functions pending at that processing element have reached at least a predetermined stage of execution; in which the given processing element is configured to inhibit the issuance of any further requests to the control circuitry until each of the group of processing elements has provided such confirmation.

公开(公告)号：US20230315510A1

公开(公告)日：2023-10-05

申请号：US18245659

申请日：2021-08-02

Applicant: ARM LIMITED

Inventor： Timothy HAYES ,  David Hennah MANSELL ,  Alasdair GRANT ,  Guy LARRI

IPC: G06F9/46 ,  G06F9/30

CPC classification number: G06F9/467 ,  G06F9/30098

Abstract: An apparatus and method are provided for handling transactions in a system employing transactional memory. The apparatus has processing circuitry for performing data processing in response to instructions, and transactional memory support circuitry for supporting execution of a transaction within a thread of data processing by the processing circuitry. The transaction comprises a sequence of instructions executed speculatively and for which the processing circuitry prevents commitment of results of those instructions until the transaction has reached a transaction end point. The transactional memory support circuitry comprises abort event detection circuitry that causes execution of the transaction to be aborted when an abort event is detected before the transaction has reached the transaction end point, and which causes abort status information to be stored for later reference when determining whether to retry execution of the transaction.

公开(公告)号：US20220382703A1

公开(公告)日：2022-12-01

申请号：US17335378

申请日：2021-06-01

Applicant: Arm Limited

Inventor： Timothy HAYES ,  Alejandro RICO CARRO ,  Tushar P. RINGE ,  Kishore Kumar JAGADEESHA

IPC: G06F13/40 ,  G06F12/0875

Abstract: An apparatus comprises an interconnect providing communication paths between agents coupled to the interconnect. A coordination agent is provided which performs an operation requiring sending a request to each of a plurality of target agents, and receiving a response from each of the target agents, the operation being unable to complete until the response has been received from each of the target agents. Storage circuitry is provided which is accessible to the coordination agent and configured to store, for each agent that the coordination agent may communicate with via the interconnect, a latency indication for communication between that agent and the coordination agent. The coordination agent is configured, prior to performing the operation, to determine a sending order in which to send the request to each of the target agents, the sending order being determined in dependence on the latency indication for each of the target agents.

公开(公告)号：US20210342248A1

公开(公告)日：2021-11-04

申请号：US17271399

申请日：2019-08-30

Applicant: Arm Limited

Inventor： Timothy HAYES ,  Giacomo GABRIELLI ,  Matthew James HORSNELL

IPC: G06F11/34 ,  G06F11/30

Abstract: An apparatus and method are provided for monitoring events in a data processing system. The apparatus has first event monitoring circuitry for monitoring occurrences of a first event within a data processing system, and for asserting a first signal to indicate every m-th occurrence of the first event, where m is an integer of 1 or more. In addition second event monitoring circuitry is used to monitor occurrences of a second event within the data processing system, and to assert a second signal to indicate every n-th occurrence of the second event, where n is an integer of 1 or more. History maintenance circuitry then maintains event history information which is updated in dependence on the asserted first and second signals. Further, history analysis circuitry is responsive to an analysis trigger to analyse the event history information in order to detect a reporting condition when the event history information indicates that a ratio between occurrences of the first event and the occurrences of the second event is outside an acceptable range. The history analysis circuitry is then responsive to detection of the reporting condition to assert a report signal. This provides a particularly efficient and effective mechanism for monitoring ratios of events within a data processing system.

公开(公告)号：US20190042253A1

公开(公告)日：2019-02-07

申请号：US15665781

申请日：2017-08-01

Applicant: ARM Limited

Inventor： Mbou EYOLE ,  Jesse Garrett BEU ,  Alejandro Martinez VICENTE ,  Timothy HAYES

IPC: G06F9/30

Abstract: An apparatus and method of operating the apparatus are provided for performing a count operation. Instruction decoder circuitry is responsive to a count instruction specifying an input data item to generate control signals to control the data processing circuitry to perform a count operation. The count operation determines a count value indicative of a number of input elements of a subset of elements in the specified input data item which have a value which matches a reference value in a reference element in a reference data item. A plurality of count operations may be performed to determine a count data item corresponding to the input data item. A register scatter storage instruction, a gather index generation instruction, and respective apparatuses responsive to them, as well as simulator implementations, are also provided.

公开(公告)号：US20190042190A1

公开(公告)日：2019-02-07

申请号：US15665715

申请日：2017-08-01

Applicant: ARM Limited

Inventor： Alejandro Martinez VICENTE ,  Jesse Garrett BEU ,  Mbou EYOLE ,  Timothy HAYES

IPC: G06F7/02 ,  G06F9/30

Abstract: An apparatus and a method of operating the apparatus are provided for performing a comparison operation to match a given sequence of values within an input vector. Instruction decoder circuitry is responsive to a string match instruction specifying a segment of an input vector to generate control signals to control the data processing circuitry to perform a comparison operation. The comparison operation determines a comparison value indicative of whether each input element of a required set of consecutive input elements of the segment has a value which matches a respective value in consecutive reference elements of the reference data item. A plurality of comparison operations may be performed to determine a match vector corresponding to the segment of the input vector to indicate the start position of the substring in the input vector. A string match instruction, as well as simulator virtual machine implementations, are also provided.