公开(公告)号：US20180144780A1

公开(公告)日：2018-05-24

申请号：US15357691

申请日：2016-11-21

Applicant: ARM Limited

Inventor： Jungtae Kwon ,  Young Suk Kim

IPC: G11C7/22 ,  G11C7/12 ,  G11C7/14

CPC classification number: G11C7/22 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/14 ,  G11C7/227 ,  G11C8/14

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a memory bank having an array of memory cells that are accessible via a selected wordline and a pair of complementary bitlines. The integrated circuit may include a dummy wordline coupled to each of the pair of complementary bitlines via a pair of coupling capacitors. The dummy wordline may mimic the selected wordline. During transitions of the pair of complementary bitlines between first and second logic states, the dummy wordline may receive coupling capacitance from the pair of complementary bitlines via the pair of coupling capacitors.

公开(公告)号：US09911510B1

公开(公告)日：2018-03-06

申请号：US15288832

申请日：2016-10-07

Applicant: ARM Limited

Inventor： Jungtae Kwon ,  Young Suk Kim ,  Vivek Nautiyal ,  Pranay Prabhat ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi ,  Satinderjit Singh ,  Lalit Gupta

IPC: G11C29/00 ,  G11C11/418 ,  G11C11/412

CPC classification number: G11C29/76 ,  G11C8/04 ,  G11C11/413 ,  G11C11/418

Abstract: Various implementations described herein are directed to an integrated circuit having a memory cell array with multiple rows of memory cells including at least one redundant row of memory cells. The memory cell array may be partitioned into multiple regions of memory cells including a first region of memory cells corresponding to a first part of the redundant row of memory cells and a second region of memory cells corresponding to a second part of the redundant row of memory cells. The integrated circuit may include wordline driver circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells. In some instances, the integrated circuit may include row shift circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells.

公开(公告)号：US09990972B1

公开(公告)日：2018-06-05

申请号：US15357691

申请日：2016-11-21

Applicant: ARM Limited

Inventor： Jungtae Kwon ,  Young Suk Kim

IPC: G11C8/00 ,  G11C7/22 ,  G11C7/12 ,  G11C7/14

CPC classification number: G11C7/22 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/14 ,  G11C7/227 ,  G11C8/14

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a memory bank having an array of memory cells that are accessible via a selected wordline and a pair of complementary bitlines. The integrated circuit may include a dummy wordline coupled to each of the pair of complementary bitlines via a pair of coupling capacitors. The dummy wordline may mimic the selected wordline. During transitions of the pair of complementary bitlines between first and second logic states, the dummy wordline may receive coupling capacitance from the pair of complementary bitlines via the pair of coupling capacitors.