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    Ramp write techniques
    1.
    发明授权
    Ramp write techniques 有权

    公开(公告)号：US12159659B2

    公开(公告)日：2024-12-03

    申请号：US17107725

    申请日：2020-11-30

    Applicant: Arm Limited

    Inventor： Supreet Jeloka ,  Mudit Bhargava ,  Pranay Prabhat ,  Fernando Garcia Redondo

    IPC: G11C11/16

    Abstract: Various implementations described herein are related to a method. The method may apply a write control voltage to a bitcell. The method may gradually ramp the write control voltage to the bitcell. The method may terminate application of the write control voltage to the bitcell when a write operation is sensed in the bitcell.

    Memory device with on-chip sacrificial memory cells
    3.
    发明授权
    Memory device with on-chip sacrificial memory cells 有权

    公开(公告)号：US11521680B2

    公开(公告)日：2022-12-06

    申请号：US17139059

    申请日：2020-12-31

    Applicant: Arm Limited

    Inventor： Fernando Garcia Redondo ,  Mudit Bhargava ,  Pranay Prabhat ,  Supreet Jeloka

    IPC: G11C11/00 ,  G11C13/00 ,  G11C11/16

    Abstract: An integrated circuit includes a primary memory array with cells switchable between first and second states. The circuit also includes sacrificial memory cells; each fabricated to be switchable between the first and second states and associated with at least one row of the primary array. A controller is configured to detect a write operation to a row of the primary array, stress a sacrificial cell associated with the row and detect a failure of the associated sacrificial cell. The sacrificial cells are fabricated to have lower write-cycle endurance than cells of the primary array or are subjected to more stress. Failure of a row of the primary array is predicted based, at least in part, on a detected failure of the associated sacrificial cell.

    Systems and Methods of Power Management
    4.
    发明申请
    Systems and Methods of Power Management 有权

    公开(公告)号：US20210208803A1

    公开(公告)日：2021-07-08

    申请号：US16735606

    申请日：2020-01-06

    Applicant: Arm Limited

    Inventor： James Edward Myers ,  Pranay Prabhat ,  Matthew James Walker ,  Parameshwarappa Anand Kumar Savanth ,  Fernando Garcia Redondo

    IPC: G06F3/06 ,  G06F1/3234 ,  G06F1/3221 ,  G06F1/3209

    Abstract: According to one implementation of the present disclosure, a method for power management is disclosed. The method includes: computing, by a central processing unit, software instructions of a software workload in an active-mode operation corresponding to a first operating point on a performance curve of a performance mode; transitioning from instances of the active-mode operation to instances of standby-mode operation of the CPU, and recording, by a time tracking element, each of a plurality of standby entry data points; transitioning from the instances of the standby-mode operation to the instances of the active-mode operation of the CPU, and recording, by the time tracking element, each of a plurality of standby exit data points; and determining a second operating point on the performance curve of the performance mode based on the recorded standby entry data points and the recorded standby exit data points.

    Digital forward body biasing in CMOS circuits
    6.
    发明授权
    Digital forward body biasing in CMOS circuits 有权

    公开(公告)号：US10181848B2

    公开(公告)日：2019-01-15

    申请号：US15418331

    申请日：2017-01-27

    Applicant: ARM Limited

    Inventor： Pranay Prabhat ,  Parameshwarappa Anand Kumar Savanth ,  James Edward Myers

    IPC: H03K17/687 ,  H01L29/10

    Abstract: Embodiments are described for digital forward body biasing CMOS circuits. In an embodiment, a power management unit limits the amount of time for which digital forward body biasing may be implemented. In another embodiment, once a CMOS circuit is put into a full digital forward body bias mode, the CMOS circuit is gradually brought back to a zero forward body bias mode. In another embodiment, charge is shared among biased transistor wells during transition intervals when transitioning from one bias mode to another.

    Periphery body biasing for memory applications
    10.
    发明授权
    Periphery body biasing for memory applications 有权

    公开(公告)号：US10586790B2

    公开(公告)日：2020-03-10

    申请号：US15942132

    申请日：2018-03-30

    Applicant: Arm Limited

    Inventor： Pranay Prabhat ,  James Edward Myers

    IPC: H01L27/02 ,  G11C11/417 ,  G11C11/412 ,  H01L27/11

    Abstract: Various implementations described herein are directed to an integrated circuit having a core array region with an array of memory devices. The integrated circuit may include a periphery region having periphery logic devices that interface with the array of memory devices. The integrated circuit may include a boundary region having one or more buffer devices coupled to body terminals of the periphery logic devices to drive the body terminals of the periphery logic devices using a body biasing signal provided by the one or more buffer devices.

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