公开(公告)号：US20240222176A1

公开(公告)日：2024-07-04

申请号：US18397549

申请日：2023-12-27

Applicant: ASM IP Holding B.V.

Inventor： Yoshiyuki Umeoka

IPC: H01L21/677 ,  H01L21/67 ,  H01L21/68 ,  H01L21/687

CPC classification number: H01L21/67745 ,  H01L21/67161 ,  H01L21/67201 ,  H01L21/67259 ,  H01L21/67706 ,  H01L21/67742 ,  H01L21/68 ,  H01L21/68707

Abstract: A wafer processing apparatus and a method thereof are presented. The apparatus comprising a first loadlock and a second loadlock, a first wafer handling chamber comprising a first robot, pass-through chamber comprising upper slots and lower slots, a second wafer handling chamber comprising a second robot, and a scheduling unit configured to schedule movements of the plurality of wafers by the first robot and the second robot, wherein the scheduling unit configured to schedule the first robot to move wafers originated from the first loadlock from the at least one intermediate chamber into the at least one first upper slot and to move wafers originated from the second loadlock from the at least one intermediate chamber into the at least one second upper slot and further configured to schedule the first robot to move a wafer originated from the first loadlock from the at least one intermediate chamber into one of the at least one second upper slot when all the at least one first upper slot are occupied by wafers and to move the wafer to the at least one first upper slot when it becomes available and schedule the first robot to move a wafer originated from the second loadlock from the at least one intermediate chamber into one of the at least one first upper slot when all the at least one second upper slot are occupied by wafers and to move the wafer to the at least one second upper slot when it becomes available.

公开(公告)号：US20240120226A1

公开(公告)日：2024-04-11

申请号：US18474953

申请日：2023-09-26

Applicant: ASM IP Holding, B.V.

Inventor： Yoshiyuki Umeoka

IPC: H01L21/677 ,  G05B19/418 ,  H01L21/67

CPC classification number: H01L21/67745 ,  G05B19/41865 ,  H01L21/67201 ,  H01L21/67276 ,  H01L21/67706 ,  H01L21/67742

Abstract: A wafer processing apparatus may be presented. The apparatus comprising a first loadlock and a second loadlock, at least one extra chambers for preprocessing or postprocessing the wafers, at least one reaction chambers configured to process the wafers, a first wafer handling chamber comprising a first robot, the first robot configured to move wafers between the first and second loadlocks and the extra chambers, a second wafer handling chamber comprising a second robot, the second robot configured to move wafers between the reaction chambers and a pass-through chamber, a pass-through chamber configured to stack wafers from both the first wafer handling chamber and the second wafer handling chamber; and a scheduling unit configured to schedule movements of the plurality of wafers by the first robot and the second robot.

公开(公告)号：US20220359246A1

公开(公告)日：2022-11-10

申请号：US17736502

申请日：2022-05-04

Applicant: ASM IP Holding B.V.

Inventor： Yoshiyuki Umeoka

IPC: H01L21/67 ,  H01L21/687 ,  H01L21/66 ,  C23C16/455 ,  C23C16/52 ,  C23C16/46 ,  C23C16/50

Abstract: Examples of a substrate treatment apparatus includes a chamber, a substrate support stage located inside the chamber, an elevation device that moves the substrate support stage up and down, a gate valve provided between the chamber and an adjacent chamber that is adjacent to the chamber, and a chamber state controller including a processor and a memory configured to cause the processor to execute a program stored in the memory, or including a dedicated circuitry, to move the elevation device and the gate valve before a next substrate treatment is performed in the chamber, in a state in which no substrate is present in the chamber.

公开(公告)号：US20220359241A1

公开(公告)日：2022-11-10

申请号：US17736691

申请日：2022-05-04

Applicant: ASM IP Holding B.V.

Inventor： Yoshiyuki Umeoka

IPC: H01L21/67 ,  H01L21/677 ,  G05B19/418

Abstract: Examples of a substrate treatment apparatus include a plurality of load ports, a front-end module adjacent to the plurality of load ports, a plurality of load lock chambers adjacent to the front-end module, the plurality of load lock chambers include a plurality of wafer housing slots, a wafer handling chamber adjacent to the plurality of load lock chambers, a first wafer transfer device in the front-end module, a second wafer transfer device in the wafer handling chamber, and a controller including a processor and a memory configured to cause the processor to execute a program stored in the memory, or including a dedicated circuitry, to issue a command to a wafer moving device to move a wafer between the plurality of load lock chambers when predetermined wafer transfer conditions are satisfied.