公开(公告)号：US20230341784A1

公开(公告)日：2023-10-26

申请号：US18016811

申请日：2021-07-14

Applicant: ASML NETHERLANDS B.V.

Inventor： Tijmen Pieter COLLIGNON ,  Pavel SMAL ,  Cyrus Emil TABERY ,  Thiago DOS SANTOS GUZELLA ,  Vahid BASTANI

IPC: G03F7/00 ,  G03F9/00

CPC classification number: G03F7/70508 ,  G03F9/7034 ,  G03F9/7026 ,  G03F7/70908 ,  G03F7/70516

Abstract: Methods and associated apparatus for identifying contamination in a semiconductor fab. The methods include determining contamination map data for a plurality of semiconductor wafers clamped to a wafer table after being processed in the semiconductor fab. Combined contamination map data is determined based, at least in part, on a combination of the contamination map data of the plurality of semiconductor wafers. The combined contamination map data is combined to reference data. The reference data include one or more values for the combined contamination map data that are indicative of contamination in one or more tools in the semiconductor fab.

公开(公告)号：US20220011683A1

公开(公告)日：2022-01-13

申请号：US17294503

申请日：2019-10-21

Applicant: ASML NETHERLANDS B.V.

Inventor： Pavel SMAL ,  Inez Marlena SOCHAL ,  Gautam SARMA

IPC: G03F9/00 ,  G03F7/20

Abstract: A method for determining a layout of mark positions across a patterning device or substrate, the method including: obtaining a model configured to model data associated with measurements performed on the patterning device or substrate at one or more mark positions; obtaining an initial mark layout including initial mark positions; reducing the initial mark layout by removal of one or more mark positions to obtain a plurality of reduced mark layouts, each reduced mark layout obtained by removal of a different mark position from the initial mark layout; determining a model uncertainty metric associated with usage of the model for each reduced mark layout out of the plurality of reduced mark layouts; and selecting one or more reduced mark layouts based on its associated model uncertainty metric.