公开(公告)号：US12265510B1

公开(公告)日：2025-04-01

申请号：US18478895

申请日：2023-09-29

Applicant: ATI Technologies ULC

Inventor： Yinan Jiang ,  Dmytro Chenchykov ,  Shaoyun Liu ,  Vignesh Chander

IPC: G06F16/00 ,  G06F16/21 ,  G06F21/64

Abstract: A computer-implemented method for ensuring processing unit hardware state integrity in live migration can include participating as a source, by a processing unit, in a live migration procedure by injecting, into a live migration data package containing a state of the processing unit, a signature verifying the state. The method can additionally include participating as a target, by the processing unit, in an additional live migration procedure migrating an additional live migration data package containing an additional state of an additional processing unit by performing an integrity check based on an additional signature, in the additional live migration data package, verifying the additional state. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20250110930A1

公开(公告)日：2025-04-03

申请号：US18478895

申请日：2023-09-29

Applicant: ATI Technologies ULC

Inventor： Yinan Jiang ,  Dmytro Chenchykov ,  Shaoyun Liu ,  Vignesh Chander

IPC: G06F16/21

Abstract: A computer-implemented method for ensuring processing unit hardware state integrity in live migration can include participating as a source, by a processing unit, in a live migration procedure by injecting, into a live migration data package containing a state of the processing unit, a signature verifying the state. The method can additionally include participating as a target, by the processing unit, in an additional live migration procedure migrating an additional live migration data package containing an additional state of an additional processing unit by performing an integrity check based on an additional signature, in the additional live migration data package, verifying the additional state. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US12169731B2

公开(公告)日：2024-12-17

申请号：US17564144

申请日：2021-12-28

Applicant: ATI TECHNOLOGIES ULC

Inventor： Yinan Jiang ,  Shaoyun Liu ,  Aranyak Mishra ,  Maria Joo

IPC: G06F9/455 ,  G06F9/38 ,  G06F9/4401

Abstract: A processing system selects a reset sequence based on a sideband connected configuration of a plurality of processing units. The processing system identifies whether the plurality of processing units is in the sideband connected configuration, so that the plurality of processing units works together on assigned operations. Based on the identification, the processing system selects and executes one of a plurality of available reset sequences. The processing system is thus able to tailor the executed reset sequence for the configuration of the plurality of processing units, thereby reducing the number of overall system resets and improving processing efficiency.

公开(公告)号：US20230401082A1

公开(公告)日：2023-12-14

申请号：US17839821

申请日：2022-06-14

Applicant: ATI Technologies ULC

Inventor： Yinan Jiang ,  Shaoyun Liu

IPC: G06F9/455 ,  G06F9/48

CPC classification number: G06F9/45558 ,  G06F9/4881 ,  G06F2009/45579

Abstract: A system and method for efficiently scheduling tasks to multiple endpoint devices are described. In various implementations, a computing system has a physical hardware topology that includes multiple endpoint devices and one or more general-purpose central processing units (CPUs). A virtualization layer is added between the hardware of the computing system and an operating system that creates a guest virtual machine (VM) with multiple endpoint devices. The guest VM utilizes a guest VM topology that is different from the physical hardware topology. The processor of an endpoint device that runs the guest VM accesses a table of latency information for one or more pairs of endpoints of the guest VM based on physical hardware topology, rather than based on the guest VM topology. The processor schedules tasks on paths between endpoint devices based on the table.