-
公开(公告)号：US12045362B2
公开(公告)日：2024-07-23
申请号：US17889956
申请日：2022-08-17
Applicant: ATI TECHNOLOGIES ULC , ADVANCED MICRO DEVICES, INC.
Inventor： Benjamin Koon Pan Chan , William Lloyd Atkinson , Tung Chuen Kwong , Guhan Krishnan
CPC classification number: G06F21/6218 , G06V10/955
Abstract: A computer vision processor in an image cluster defines a fenced memory region (FMR) that controls access to image data stored in a first portion of a trusted memory region (TMR). The computer vision processor receives FMR requests from an application implemented in a processing cluster. The FMR requests are to access the image data in the first portion of the TMR. The computer vision processor selectively allows the requesting application to access the image data. In some cases, the computer vision processor acquires the image data and stores the image data in the first portion of the TMR, such as buffers in the TMR. A data fabric selectively permits the image processing application to access the data stored in the TMR based on whether the image cluster has opened or closed the FMR for the portion of the TMR.
-
公开(公告)号：US11954792B2
公开(公告)日：2024-04-09
申请号：US17408034
申请日：2021-08-20
Applicant: ATI Technologies ULC
Inventor： Benjamin Koon Pan Chan , William Lloyd Atkinson , Clarence Ip , Tung Chuen Kwong
CPC classification number: G06T15/205 , G06F15/7814 , G06T1/20 , G09G5/14 , G09G2320/0261
Abstract: Systems, apparatuses, and methods for performing real-time video rendering with performance guaranteed power management are disclosed. A system includes at least a software driver, a power management unit, and a plurality of processing elements for performing rendering tasks. The system receives inputs which correspond to rendering tasks which need to be performed. The software driver monitors the inputs that are received and the number of rendering tasks to which they correspond. The software driver also monitors the amount of time remaining until the next video synchronization signal. The software driver determines which performance setting will minimize power consumption while still allowing enough time to finish the rendering tasks for the current frame before the next video synchronization signal. Then, the software driver causes the power management unit to provide this performance setting to the plurality of processing elements as they perform the rendering tasks for the current frame.
-
公开(公告)号：US10824436B2
公开(公告)日：2020-11-03
申请号：US16219273
申请日：2018-12-13
Applicant: ATI TECHNOLOGIES ULC
Inventor： Benjamin Koon Pan Chan , William Lloyd Atkinson
IPC: G06F9/44 , G06F9/4401 , G06F9/38 , G06F9/445 , G06F9/50
Abstract: A hybrid co-processing system including both complex instruction set computer (CISC) architecture-based processing clusters and reduced instruction set computer (RISC) architecture-based processing clusters includes a parser to derive from a hardware configuration specific to the CISC architecture, such as an ACPI table, a device tree specific to the RISC architecture for booting. The hardware configuration information indicated by the device tree is specific to the RISC architecture, and in different cases includes more, less, or revised information than a corresponding ACPI table for the same hybrid co-processing system.
-
公开(公告)号：US11443051B2
公开(公告)日：2022-09-13
申请号：US16228349
申请日：2018-12-20
Applicant: ATI TECHNOLOGIES ULC , ADVANCED MICRO DEVICES, INC.
Inventor： Benjamin Koon Pan Chan , William Lloyd Atkinson , Tung Chuen Kwong , Guhan Krishnan
Abstract: A computer vision processor in an image cluster defines a fenced memory region (FMR) that controls access to image data stored in a first portion of a trusted memory region (TMR). The computer vision processor receives FMR requests from an application implemented in a processing cluster. The FMR requests are to access the image data in the first portion of the TMR. The computer vision processor selectively allows the requesting application to access the image data. In some cases, the computer vision processor acquires the image data and stores the image data in the first portion of the TMR, such as buffers in the TMR. A data fabric selectively permits the image processing application to access the data stored in the TMR based on whether the image cluster has opened or closed the FMR for the portion of the TMR.
-
公开(公告)号：US20210383596A1
公开(公告)日：2021-12-09
申请号：US17408034
申请日：2021-08-20
Applicant: ATI Technologies ULC
Inventor： Benjamin Koon Pan Chan , William Lloyd Atkinson , Clarence Ip , Tung Chuen Kwong
Abstract: Systems, apparatuses, and methods for performing real-time video rendering with performance guaranteed power management are disclosed. A system includes at least a software driver, a power management unit, and a plurality of processing elements for performing rendering tasks. The system receives inputs which correspond to rendering tasks which need to be performed. The software driver monitors the inputs that are received and the number of rendering tasks to which they correspond. The software driver also monitors the amount of time remaining until the next video synchronization signal. The software driver determines which performance setting will minimize power consumption while still allowing enough time to finish the rendering tasks for the current frame before the next video synchronization signal. Then, the software driver causes the power management unit to provide this performance setting to the plurality of processing elements as they perform the rendering tasks for the current frame.
-
Patent Agency Ranking
公开(公告)号：US20210081328A1
公开(公告)日：2021-03-18
申请号：US17105331
申请日：2020-11-25
Applicant: ATI Technologies ULC
Inventor： Tung Chuen Kwong , Benjamin Koon Pan Chan , William Lloyd Atkinson
IPC: G06F12/1009 , G06F9/54 , G06F12/02
Abstract: Systems, apparatuses, and methods for implementing a unified kernel virtual address space for heterogeneous computing are disclosed. A system includes at least a first subsystem running a first kernel, an input/output memory management unit (IOMMU), and a second subsystem running a second kernel. In order to share a memory buffer between the two subsystems, the first subsystem allocates a block of memory in part of the system memory controlled by the first subsystem. A first mapping is created from a first logical address of the kernel address space of the first subsystem to the block of memory. Then, the IOMMU creates a second mapping to map the physical address of that block of memory from a second logical address of the kernel address space of the second subsystem. These mappings allow the first and second subsystems to share buffer pointers which reference the block of memory.
-
公开(公告)号：US11960410B2
公开(公告)日：2024-04-16
申请号：US17105331
申请日：2020-11-25
Applicant: ATI Technologies ULC
Inventor： Tung Chuen Kwong , Benjamin Koon Pan Chan , William Lloyd Atkinson
IPC: G06F12/1009 , G06F9/54 , G06F12/02
CPC classification number: G06F12/1009 , G06F9/544 , G06F9/545 , G06F12/0246
Abstract: Systems, apparatuses, and methods for implementing a unified kernel virtual address space for heterogeneous computing are disclosed. A system includes at least a first subsystem running a first kernel, an input/output memory management unit (IOMMU), and a second subsystem running a second kernel. In order to share a memory buffer between the two subsystems, the first subsystem allocates a block of memory in part of the system memory controlled by the first subsystem. A first mapping is created from a first logical address of the kernel address space of the first subsystem to the block of memory. Then, the IOMMU creates a second mapping to map the physical address of that block of memory from a second logical address of the kernel address space of the second subsystem. These mappings allow the first and second subsystems to share buffer pointers which reference the block of memory.
-
公开(公告)号：US20230110765A1
公开(公告)日：2023-04-13
申请号：US17889956
申请日：2022-08-17
Applicant: ATI TECHNOLOGIES ULC , ADVANCED MICRO DEVICES, INC.
Inventor： Benjamin Koon Pan CHAN , William Lloyd Atkinson , Tung Chuen Kwong , Guhan Krishnan
Abstract: A computer vision processor in an image cluster defines a fenced memory region (FMR) that controls access to image data stored in a first portion of a trusted memory region (TMR). The computer vision processor receives FMR requests from an application implemented in a processing cluster. The FMR requests are to access the image data in the first portion of the TMR. The computer vision processor selectively allows the requesting application to access the image data. In some cases, the computer vision processor acquires the image data and stores the image data in the first portion of the TMR, such as buffers in the TMR. A data fabric selectively permits the image processing application to access the data stored in the TMR based on whether the image cluster has opened or closed the FMR for the portion of the TMR.
-
公开(公告)号：US11100698B2
公开(公告)日：2021-08-24
申请号：US16457179
申请日：2019-06-28
Applicant: ATI Technologies ULC
Inventor： Benjamin Koon Pan Chan , William Lloyd Atkinson , Clarence Ip , Tung Chuen Kwong
Abstract: Systems, apparatuses, and methods for performing real-time video rendering with performance guaranteed power management are disclosed. A system includes at least a software driver, a power management unit, and a plurality of processing elements for performing rendering tasks. The system receives inputs which correspond to rendering tasks which need to be performed. The software driver monitors the inputs that are received and the number of rendering tasks to which they correspond. The software driver also monitors the amount of time remaining until the next video synchronization signal. The software driver determines which performance setting will minimize power consumption while still allowing enough time to finish the rendering tasks for the current frame before the next video synchronization signal. Then, the software driver causes the power management unit to provide this performance setting to the plurality of processing elements as they perform the rendering tasks for the current frame.
-
公开(公告)号：US10853263B1
公开(公告)日：2020-12-01
申请号：US16519311
申请日：2019-07-23
Applicant: ATI Technologies ULC
Inventor： Tung Chuen Kwong , Benjamin Koon Pan Chan , William Lloyd Atkinson
IPC: G06F12/02 , G06F12/1009 , G06F9/54
Abstract: Systems, apparatuses, and methods for implementing a unified kernel virtual address space for heterogeneous computing are disclosed. A system includes at least a first subsystem running a first kernel, an input/output memory management unit (IOMMU), and a second subsystem running a second kernel. In order to share a memory buffer between the two subsystems, the first subsystem allocates a block of memory in part of the system memory controlled by the first subsystem. A first mapping is created from a first logical address of the kernel address space of the first subsystem to the block of memory. Then, the IOMMU creates a second mapping to map the physical address of that block of memory from a second logical address of the kernel address space of the second subsystem. These mappings allow the first and second subsystems to share buffer pointers which reference the block of memory.
-
-
-
-
-
-
-
-
-
Search Results
10
records
(took 0.013 seconds)
