公开(公告)号：US20200279538A1

公开(公告)日：2020-09-03

申请号：US16289260

申请日：2019-02-28

Applicant: ATI Technologies ULC

Inventor： Keith Lee ,  David I. J. Glen ,  Jie Zhou ,  Yuxin Chen

IPC: G09G5/06

Abstract: Systems, apparatuses, and methods for reducing three dimensional (3D) lookup table (LUT) interpolation error while minimizing on-chip storage are disclosed. A processor generates a plurality of mappings from a first gamut to a second gamut at locations interspersed throughout a 3D representation of the pixel component space. For example, in one implementation, the processor calculates mappings for 17×17×17 vertices within the 3D representation. Other implementations can include other numbers of vertices. Rather than increasing the number of vertices to reduce interpolation error, the processor calculates mappings for centroids of the sub-cubes defined by the vertices within the 3D representation of the first gamut. This results in a smaller increase to the LUT size as compared to increasing the number of vertices. The centroid mappings are used for performing tetrahedral interpolation to map source pixels in the first gamut into the second gamut with a reduced amount of interpolation error.

公开(公告)号：US10453171B2

公开(公告)日：2019-10-22

申请号：US15469299

申请日：2017-03-24

Applicant: ATI TECHNOLOGIES ULC

Inventor： Yuxin Chen ,  Chun-Chin Yeh

IPC: G06T1/60 ,  G09G5/06 ,  G06F12/02

Abstract: A processor is configured to store color component values associated with a first subset of vertices of a three-dimensional (3-D) look up table (LUT) in a first subset of memory elements. The color component values are defined according to a destination gamut. A data select module is configured to access the color component values from the first subset of the memory elements concurrently with the processor storing color component values associated with a second subset of the vertices of the 3-D LUT in a second subset of the memory elements. The data select module is configured to access the color component values from the first and second subsets of the memory elements in response to the processor storing the color component values associated with the second subset of the vertices of the 3-D LUT in the second subset of the memory elements. This process can be extended to additional subsets.

公开(公告)号：US12190847B2

公开(公告)日：2025-01-07

申请号：US17407981

申请日：2021-08-20

Applicant: ATI Technologies ULC

Inventor： Keith Lee ,  David I. J. Glen ,  Jie Zhou ,  Yuxin Chen

IPC: G09G5/02 ,  G09G5/06

Abstract: Systems, apparatuses, and methods for reducing three dimensional (3D) lookup table (LUT) interpolation error while minimizing on-chip storage are disclosed. A processor generates a plurality of mappings from a first gamut to a second gamut at locations interspersed throughout a 3D representation of the pixel component space. For example, in one implementation, the processor calculates mappings for 17×17×17 vertices within the 3D representation. Other implementations can include other numbers of vertices. Rather than increasing the number of vertices to reduce interpolation error, the processor calculates mappings for centroids of the sub-cubes defined by the vertices within the 3D representation of the first gamut. This results in a smaller increase to the LUT size as compared to increasing the number of vertices. The centroid mappings are used for performing tetrahedral interpolation to map source pixels in the first gamut into the second gamut with a reduced amount of interpolation error.

公开(公告)号：US11100889B2

公开(公告)日：2021-08-24

申请号：US16289260

申请日：2019-02-28

Applicant: ATI Technologies ULC

Inventor： Keith Lee ,  David I. J. Glen ,  Jie Zhou ,  Yuxin Chen

IPC: G09G5/02 ,  G09G5/06

Abstract: Systems, apparatuses, and methods for reducing three dimensional (3D) lookup table (LUT) interpolation error while minimizing on-chip storage are disclosed. A processor generates a plurality of mappings from a first gamut to a second gamut at locations interspersed throughout a 3D representation of the pixel component space. For example, in one implementation, the processor calculates mappings for 17×17×17 vertices within the 3D representation. Other implementations can include other numbers of vertices. Rather than increasing the number of vertices to reduce interpolation error, the processor calculates mappings for centroids of the sub-cubes defined by the vertices within the 3D representation of the first gamut. This results in a smaller increase to the LUT size as compared to increasing the number of vertices. The centroid mappings are used for performing tetrahedral interpolation to map source pixels in the first gamut into the second gamut with a reduced amount of interpolation error.

公开(公告)号：US20210383772A1

公开(公告)日：2021-12-09

申请号：US17407981

申请日：2021-08-20

Applicant: ATI Technologies ULC

Inventor： Keith Lee ,  David I. J. Glen ,  Jie Zhou ,  Yuxin Chen

IPC: G09G5/06

Abstract: Systems, apparatuses, and methods for reducing three dimensional (3D) lookup table (LUT) interpolation error while minimizing on-chip storage are disclosed. A processor generates a plurality of mappings from a first gamut to a second gamut at locations interspersed throughout a 3D representation of the pixel component space. For example, in one implementation, the processor calculates mappings for 17×17×17 vertices within the 3D representation. Other implementations can include other numbers of vertices. Rather than increasing the number of vertices to reduce interpolation error, the processor calculates mappings for centroids of the sub-cubes defined by the vertices within the 3D representation of the first gamut. This results in a smaller increase to the LUT size as compared to increasing the number of vertices. The centroid mappings are used for performing tetrahedral interpolation to map source pixels in the first gamut into the second gamut with a reduced amount of interpolation error.

公开(公告)号：US10424269B2

公开(公告)日：2019-09-24

申请号：US15388663

申请日：2016-12-22

Applicant: ATI TECHNOLOGIES ULC

Inventor： Yuxin Chen ,  David Glen ,  Yee Shun Chan

IPC: G09G5/06 ,  G09G5/02 ,  G09G5/397

Abstract: A three-dimensional (3-D) look up table (LUT) can be accessed using an address decoder to identify a plurality of vertices in the 3-D LUT based on a number (m) of most significant bits (MSBs) of three coordinate values representative of a first color and a non-zero integer (p). The three coordinate values are determined by a source gamut. One or more memories store component values representative of a plurality of second colors determined by a destination gamut. The component values are stored at memory locations associated with the plurality of vertices. An interpolator maps the input color to an output color in the destination gamut based on the component values.

公开(公告)号：US10242647B2

公开(公告)日：2019-03-26

申请号：US15442259

申请日：2017-02-24

Applicant: ATI TECHNOLOGIES ULC

Inventor： Yuxin Chen

IPC: G09G5/06 ,  G06T11/00 ,  G06F7/38 ,  H04N1/60

Abstract: A data segmenter is configured to determine indices using numbers of most significant bits (MSBs) of fractional values of floating-point representations of component values of an input color that are selected based on exponent values of the floating-point representations. The component values are defined according to a source gamut. The data segmenter is also configured to determine offsets associated with the indices using subsets of the fractional values. An interpolator configured to map the input color to an output color defined according to a destination gamut based on a location in a three-dimensional (3-D) look up table (LUT) indicated by the indices and offsets.

公开(公告)号：US20240223768A1

公开(公告)日：2024-07-04

申请号：US18089928

申请日：2022-12-28

Applicant: ATI TECHNOLOGIES ULC

Inventor： Yuxin Chen ,  Ying Luo ,  Edward Harold ,  Shu-Hsien Wu ,  Xinghai Li ,  Razvan F. Dan-Dobre ,  Min Wang ,  Jianbin Xiao ,  Amal Khailtash ,  Yin Xia Yang ,  Kai Sun

IPC: H04N19/137 ,  H04N19/105 ,  H04N19/176 ,  H04N19/53

CPC classification number: H04N19/137 ,  H04N19/105 ,  H04N19/176 ,  H04N19/53

Abstract: The present disclosure provides techniques for implementing a hierarchical and partitional integer motion estimation search (IMES) architecture using a search engine that is configurable based on a content of a plurality of frames in a video sequence. For example, the techniques include identifying, based on the plurality of frames, one or more search parameters for the hierarchical and partitional motion estimation, where the one or more search parameters are based on a content indicative of motion features tracked across the video sequence. The hierarchical and partitional motion estimation, which includes at least one decimated motion estimation search followed by a full-pixel level search, is performed based on the one or more identified search parameters to determine an integer (or pixel-level) motion vector.