公开(公告)号：US20240012970A1

公开(公告)日：2024-01-11

申请号：US17861623

申请日：2022-07-11

Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES, INC.

Inventor： David Akselrod ,  Alexander Kaganov ,  David M. Dahle ,  Tyrone Huang

IPC: G06F30/3308

CPC classification number: G06F30/3308 ,  G06F2119/18

Abstract: Techniques for implementing an overstress design for verification that reduce production and verification time by enabling a verification system to perform verification of components of a circuit design selectively, accurately, and exhaustively under extreme stress scenarios are disclosed. Circuit nodes in an emulation model are selected and overstress is provided to the nodes such that behavior of the circuit under such extreme stress scenarios is readily observable, enabling designers to produce circuits that are more secure, reliable, and resilient in case of failures. Overstress is provided to the node to enable verification of the emulation model without having to design complex test signal representations to produce extreme stress conditions. A request for manufacture is generated including aspects of the emulation model to enable verification of a fabricated circuit in a similar or identical manner to those used to verify the emulation model.