公开(公告)号：US20240037312A1

公开(公告)日：2024-02-01

申请号：US18087025

申请日：2022-12-22

Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES, INC.

Inventor： David Akselrod ,  Tassanee Payakapan ,  Arie Margulis ,  Chad Robinson

IPC: G06F30/398

CPC classification number: G06F30/398

Abstract: Techniques for implementing selective scan insertion and verification that reduce production and verification time by enabling a test harness to insert and test scan chains are disclosed. Circuit nodes in a system model are selected and scan insertion is provided at the selected nodes. Selective scan insertion can be performed quickly and, in some implementations, automatedly to enable verification of correspondence of different system models or one or more system models and fabricated circuits. A request for manufacture may be generated including aspects of the system model to enable verification of a fabricated circuit in a similar or identical manner to those used to verify the system model.

公开(公告)号：US20240012970A1

公开(公告)日：2024-01-11

申请号：US17861623

申请日：2022-07-11

Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES, INC.

Inventor： David Akselrod ,  Alexander Kaganov ,  David M. Dahle ,  Tyrone Huang

IPC: G06F30/3308

CPC classification number: G06F30/3308 ,  G06F2119/18

Abstract: Techniques for implementing an overstress design for verification that reduce production and verification time by enabling a verification system to perform verification of components of a circuit design selectively, accurately, and exhaustively under extreme stress scenarios are disclosed. Circuit nodes in an emulation model are selected and overstress is provided to the nodes such that behavior of the circuit under such extreme stress scenarios is readily observable, enabling designers to produce circuits that are more secure, reliable, and resilient in case of failures. Overstress is provided to the node to enable verification of the emulation model without having to design complex test signal representations to produce extreme stress conditions. A request for manufacture is generated including aspects of the emulation model to enable verification of a fabricated circuit in a similar or identical manner to those used to verify the emulation model.

公开(公告)号：US20230342528A1

公开(公告)日：2023-10-26

申请号：US17990005

申请日：2022-11-18

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： David Akselrod ,  Shi Han Zhang ,  Chun Fung Lam

IPC: G06F30/3308 ,  G06F30/3323 ,  G06N20/00

CPC classification number: G06F30/3308 ,  G06F30/3323 ,  G06N20/00

Abstract: Techniques for implementing a mixed signal feedback design for verification that reduce production and verification time by enabling piecemeal verification of components of a circuit design selectively, accurately, and exhaustively before a final, overall circuit design is completed are disclosed. Circuit nodes in an emulation model are selected and mixed signal feedback is provided to the nodes in response to signals detected at the nodes such that behavior of unavailable or unverified components to be located at the nodes can be simulated. Mixed signal feedback can be provided to the node to enable verification of the emulation model without having to wait for the unverified or unavailable components to be provided or verified. A request for manufacture may be generated including aspects of the emulation model to enable verification of a fabricated circuit in a similar or identical manner to those used to verify the emulation model.

公开(公告)号：US20230419006A1

公开(公告)日：2023-12-28

申请号：US17846341

申请日：2022-06-22

Applicant: ATI TECHNOLOGIES ULC

Inventor： David Akselrod

IPC: G06F30/3308 ,  G06F30/27

CPC classification number: G06F30/3308 ,  G06F30/27

Abstract: Techniques for implementing a smart feedback design for verification that reduce production and verification time by enabling a verification system to perform piecemeal verification of components of a circuit design selectively, accurately, and exhaustively before a final, overall circuit design is completed are disclosed. Circuit nodes in an emulation model are selected and smart feedback is provided to the nodes in response to signals detected at the nodes such that behavior of unavailable or unverified components to be located at the nodes can be simulated. Smart feedback can be provided to the node to enable verification of the emulation model without having to wait for the unverified or unavailable components to be provided or verified. A request for manufacture may be generated including aspects of the emulation model to enable verification of a fabricated circuit in a similar or identical manner to those used to verify the emulation model.