公开(公告)号：US08811737B2

公开(公告)日：2014-08-19

申请号：US13954148

申请日：2013-07-30

Applicant: ATI Technologies ULC

Inventor： Konstantine Iourcha ,  Andrew S. C. Pomianowski ,  Raja Koduri

IPC: G06K9/36

CPC classification number: G06T15/04 ,  H04N19/96

Abstract: Embodiments of the present invention are directed to a method and apparatus for block based image compression with multiple non-uniform block encodings. In one embodiment, an image is divided into blocks of pixels. In one embodiment the blocks are four pixels by four pixels, but other block sizes are used in other embodiments. In one embodiment, a block of pixels in the original image is compressed using two different methods to produce a first and second compressed block. Thus, each block in the original image is represented by two, typically different, compressed blocks. In one embodiment, color associated with a pixel is determined by combining the compressed information about the pixel in the first compressed block with information about the pixel in the second compressed block. In another embodiment, global information about the image is combined with the information in the first and second compressed blocks.

Abstract translation: 本发明的实施例涉及一种用于具有多个非均匀块编码的基于块的图像压缩的方法和装置。 在一个实施例中，图像被划分成像素块。 在一个实施例中，块是四像素乘四像素，但在其他实施例中使用其他块大小。 在一个实施例中，使用两种不同的方法来压缩原始图像中的像素块以产生第一和第二压缩块。 因此，原始图像中的每个块由两个通常不同的压缩块表示。 在一个实施例中，通过将关于第一压缩块中的像素的压缩信息与关于第二压缩块中的像素的信息组合来确定与像素相关联的颜色。 在另一个实施例中，关于图像的全局信息与第一和第二压缩块中的信息组合。

公开(公告)号：US11100004B2

公开(公告)日：2021-08-24

申请号：US14747944

申请日：2015-06-23

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Gongxian Jeffrey Cheng ,  Mark Fowler ,  Philip J. Rogers ,  Benjamin T. Sander ,  Anthony Asaro ,  Mike Mantor ,  Raja Koduri

IPC: G06F12/1009

Abstract: A processor uses the same virtual address space for heterogeneous processing units of the processor. The processor employs different sets of page tables for different types of processing units, such as a CPU and a GPU, wherein a memory management unit uses each set of page tables to translate virtual addresses of the virtual address space to corresponding physical addresses of memory modules associated with the processor. As data is migrated between memory modules, the physical addresses in the page tables can be updated to reflect the physical location of the data for each processing unit.

公开(公告)号：US20130315481A1

公开(公告)日：2013-11-28

申请号：US13954148

申请日：2013-07-30

Applicant: ATI Technologies ULC

Inventor： Konstantine Iourcha ,  Andrew S.C. Pomianowski ,  Raja Koduri

IPC: G06T15/04

CPC classification number: G06T15/04 ,  H04N19/96

Abstract: Embodiments of the present invention are directed to a method and apparatus for block based image compression with multiple non-uniform block encodings. In one embodiment, an image is divided into blocks of pixels. In one embodiment the blocks are four pixels by four pixels, but other block sizes are used in other embodiments. In one embodiment, a block of pixels in the original image is compressed using two different methods to produce a first and second compressed block. Thus, each block in the original image is represented by two, typically different, compressed blocks. In one embodiment, color associated with a pixel is determined by combining the compressed information about the pixel in the first compressed block with information about the pixel in the second compressed block. In another embodiment, global information about the image is combined with the information in the first and second compressed blocks.

公开(公告)号：US08781260B2

公开(公告)日：2014-07-15

申请号：US13869743

申请日：2013-04-24

Applicant: ATI Technologies ULC

Inventor： James Hunkins ,  Raja Koduri

IPC: G06K9/54

CPC classification number: G06F15/16 ,  G06F3/14 ,  G09G5/006 ,  G09G5/363 ,  G09G2360/06

Abstract: The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. Additionally, an interlink module is coupled to receive processed data corresponding to the frames from each of the multiple processors. The interlink module selects pixels of the frames from the processed data of one of the processors based on a predetermined pixel characteristic and outputs the frames that include the selected pixels.

Abstract translation: 系统和方法包括每个耦合以接收命令和数据的多个处理器，其中命令和/或数据对应于包括多个像素的视频帧。 另外，互连模块被耦合以接收对应于来自多个处理器中的每一个的帧的处理的数据。 互连模块基于预定的像素特性从一个处理器的处理数据中选择帧的像素，并输出包括所选择的像素的帧。

公开(公告)号：US20160378674A1

公开(公告)日：2016-12-29

申请号：US14747944

申请日：2015-06-23

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Gongxian Jeffrey Cheng ,  Mark Fowler ,  Philip J. Rogers ,  Benjamin T. Sander ,  Anthony Asaro ,  Mike Mantor ,  Raja Koduri

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F12/1072 ,  G06F12/1081 ,  G06F15/163 ,  G06F2212/1016 ,  G06F2212/151 ,  G06F2212/152 ,  G06F2212/251

Abstract: A processor uses the same virtual address space for heterogeneous processing units of the processor. The processor employs different sets of page tables for different types of processing units, such as a CPU and a GPU, wherein a memory management unit uses each set of page tables to translate virtual addresses of the virtual address space to corresponding physical addresses of memory modules associated with the processor. As data is migrated between memory modules, the physical addresses in the page tables can be updated to reflect the physical location of the data for each processing unit.

Abstract translation: 处理器对处理器的异构处理单元使用相同的虚拟地址空间。 处理器对不同类型的处理单元（例如CPU和GPU）采用不同的页表，其中存储器管理单元使用每组页表来将虚拟地址空间的虚拟地址转换为存储器模块的相应物理地址 与处理器相关联。 随着数据在内存模块之间迁移，可以更新页表中的物理地址，以反映每个处理单元的数据的物理位置。