公开(公告)号：US20160210156A1

公开(公告)日：2016-07-21

申请号：US14771925

申请日：2014-03-03

Applicant: ATONARP INC.

Inventor： Tomoyoshi SATO ,  Prakash Sreedhar MURTHY ,  Takeshi SATO

IPC: G06F9/44 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F9/4401 ,  G06F13/404 ,  G06F13/4282 ,  H03K19/17748

Abstract: A netlist converter, which generates configuration information for reconfiguring a reconfigurable logic operation unit, includes: a mapping unit that enumerates k-feasible cuts where the number of nodes after cutting is an integer k or fewer, out of all cuts for each node included in a netlist generated based on a specification to be processed in the logic operation unit; and a generating unit that generates configuration information including element reconfiguration information that reconfigures elements by selecting cuts assigned to the elements out of the enumerated k-feasible cuts and channel reconfiguration information for reconfiguring the data transfer channels to realize the netlist by connecting the reconfigured elements.

Abstract translation: 生成用于重新配置可重配置逻辑运算单元的配置信息的网表转换器包括：映射单元，其枚举k可行剪切，其中切割后的节点数为整数k以下， 基于要在逻辑运算单元中处理的规格生成的网表; 以及生成单元，其生成包括元件重新配置信息的配置信息，所述元件重新配置信息通过从所列举的k-可行切割中选择分配给所述元素的切割和信道重配置信息来重新配置元素，用于通过连接所述重新配置的元件来重新配置所述数据传送通道以实现所述网表。

公开(公告)号：US20160020771A1

公开(公告)日：2016-01-21

申请号：US14771570

申请日：2014-03-03

Applicant: ATONARP INC.

Inventor： Tomoyoshi SATO

IPC: H03K19/177 ,  G11C7/22

CPC classification number: H03K19/1776 ,  G11C7/22 ,  H03K19/173 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744

Abstract: A data processing device includes a data processing unit including a plurality of elements and wiring groups that connect the plurality of elements, wherein respective elements in the plurality of elements include: a logic element; an acquisition unit that switches on and off an input side of the logic element for any wire out of the wiring groups on a cycle-by-cycle basis to latch input data; and a post unit that switches on and off an output side of the logic element for any wire out of the wiring groups on a cycle-by-cycle basis, and the data processing unit also includes a timing control unit that controls logic executed by the logic element and functions of the acquisition unit and the post unit on a cycle-by-cycle basis.

Abstract translation: 数据处理装置包括：数据处理单元，包括连接多个元件的多个元件和布线组，其中多个元件中的各个元件包括：逻辑元件; 采集单元，用于逐周期地接通和断开布线组中的任何线路的逻辑元件的输入侧，以锁存输入数据; 以及一个后置单元，用于逐周期地接通和断开逻辑元件的输出侧的任何线路，并且数据处理单元还包括定时控制单元，其控制由 采集单元和后置单元的逻辑元件和功能逐个循环。