公开(公告)号：US11361907B2

公开(公告)日：2022-06-14

申请号：US16751345

申请日：2020-01-24

Applicant: AVX Corporation

Inventor： Marianne Berolini ,  Jeffrey A. Horn ,  Richard C. VanAlstine

IPC: H01G4/30 ,  H01G4/232 ,  H01G4/12 ,  H01G2/06 ,  H01G4/012

Abstract: A multilayer capacitor may include a monolithic body including a plurality of dielectric layers. A first external terminal may be disposed along a first end, and a second external terminal may be disposed along a second end of the capacitor. The external terminals may include respective bottom portions that extend along a bottom surface of the capacitor. The bottom portions of the external terminals may be spaced apart by a bottom external terminal spacing distance. A bottom shield electrode may be arranged within the monolithic body between a plurality of active electrodes and the bottom surface of the capacitor. The bottom shield electrode may be spaced apart from the bottom surface of the capacitor by a bottom-shield-to-bottom distance that may range from about 3 microns to about 100 microns. A ratio of a length of the capacitor to the bottom external terminal spacing distance may be less than about 4.

公开(公告)号：US20200243264A1

公开(公告)日：2020-07-30

申请号：US16751299

申请日：2020-01-24

Applicant: AVX Corporation

Inventor： Marianne Berolini ,  Jeffrey A. Horn ,  Richard C. VanAlstine

IPC: H01G4/232 ,  H01G4/12 ,  H01G4/012 ,  H01G2/06 ,  G01R31/01 ,  H01G4/30

Abstract: The present invention is directed to a multilayer ceramic capacitor that includes a plurality of active electrodes and at least one shield electrode that are each arranged within a monolithic body and parallel with a longitudinal direction. The capacitor may exhibit a first insertion loss value at a test frequency, which may be greater than about 2 GHz, in a first orientation relative to the mounting surface. The capacitor may exhibit a second insertion loss value at about the test frequency in a second orientation relative to the mounting surface and the capacitor is rotated 90 degrees or more about the longitudinal direction with respect to the first orientation. The longitudinal direction of the capacitor may be parallel with the mounting surface in each of the first and second orientations. The second insertion loss value may differ from the first insertion loss value by at least about 0.3 dB.

公开(公告)号：US20200243260A1

公开(公告)日：2020-07-30

申请号：US16751311

申请日：2020-01-24

Applicant: AVX Corporation

Inventor： Marianne Berolini ,  Jeffrey A. Horn ,  Richard C. VanAlstine

IPC: H01G4/012 ,  H01G4/30 ,  H01G4/232

Abstract: The present invention is directed to a multilayer ceramic capacitor. A plurality of active electrodes may be arranged within a monolithic body of the capacitor and parallel with a longitudinal direction. A first shield electrode may be arranged within the monolithic body and parallel with the longitudinal direction. The first shield electrode may be connected with a first external terminal. The first shield electrode may have a first longitudinal edge and a second longitudinal edge that are each aligned with the lateral direction and face away from the first external terminal. The second longitudinal edge may be offset in the longitudinal direction from the first longitudinal edge by a shield electrode offset distance. A second shield electrode may be connected with a second external terminal. The second shield electrode may be approximately aligned with the first shield electrode in the Z-direction.

公开(公告)号：US11270842B2

公开(公告)日：2022-03-08

申请号：US16751289

申请日：2020-01-24

Applicant: AVX Corporation

Inventor： Marianne Berolini ,  Jeffrey A. Horn ,  Richard C. VanAlstine

IPC: H01G4/012 ,  H01G4/30

Abstract: A multilayer ceramic capacitor may include a monolithic body including a plurality of dielectric layers and a plurality of electrode regions. The plurality of electrode regions can include a dielectric region, an active electrode region, and a shield electrode region. The active electrode region may be located between the dielectric region and the shield electrode region in a Z-direction. The dielectric region may extend from the active electrode region to the top surface of the broadband multilayer ceramic capacitor. The capacitor may include a plurality of active electrodes arranged within the active electrode region and at least one shield electrode arranged within the shield electrode region. The dielectric region may be free of electrode layers that extend greater than 25% of a length of the capacitor. A ratio of a capacitor thickness to a thickness of the dielectric region may be less than about 20.

公开(公告)号：US11195656B2

公开(公告)日：2021-12-07

申请号：US16751323

申请日：2020-01-24

Applicant: AVX Corporation

Inventor： Marianne Berolini ,  Jeffrey A. Horn ,  Richard C. VanAlstine

IPC: H01G4/012 ,  H01G4/12 ,  H01G4/30 ,  H01G4/232

Abstract: A broadband multilayer ceramic capacitor may include a monolithic body including a plurality of dielectric layers stacked in the Z-direction, a first external terminal, and a second external terminal. A plurality of active electrodes, a bottom shield electrode, and a top shield electrode may be arranged within the monolithic body. The top shield electrode may be positioned between the active electrodes and a top surface of the capacitor and spaced apart from the top surface of the capacitor by a top-shield-to-top distance. A bottom shield electrode may be positioned between the active electrodes and the bottom surface of the capacitor and spaced apart from the bottom surface of the capacitor by a bottom-shield-to-bottom distance. A ratio of the top-shield-to-top distance to the bottom-shield-to-bottom distance may be between about 0.8 and about 1.2. The bottom-shield-to-bottom distance may range from about 8 microns to about 100 microns.

公开(公告)号：US20200243265A1

公开(公告)日：2020-07-30

申请号：US16751345

申请日：2020-01-24

Applicant: AVX Corporation

Inventor： Marianne Berolini ,  Jeffrey A. Horn ,  Richard C. VanAlstine

IPC: H01G4/30 ,  H01G4/232 ,  H01G4/012 ,  H01G2/06 ,  H01G4/12

Abstract: A multilayer capacitor may include a monolithic body including a plurality of dielectric layers. A first external terminal may be disposed along a first end, and a second external terminal may be disposed along a second end of the capacitor. The external terminals may include respective bottom portions that extend along a bottom surface of the capacitor. The bottom portions of the external terminals may be spaced apart by a bottom external terminal spacing distance. A bottom shield electrode may be arranged within the monolithic body between a plurality of active electrodes and the bottom surface of the capacitor. The bottom shield electrode may be spaced apart from the bottom surface of the capacitor by a bottom-shield-to-bottom distance that may range from about 3 microns to about 100 microns. A ratio of a length of the capacitor to the bottom external terminal spacing distance may be less than about 4.

公开(公告)号：US20190080851A1

公开(公告)日：2019-03-14

申请号：US16124616

申请日：2018-09-07

Applicant: AVX Corporation

Inventor： Craig W. Nies ,  Andrew P. Ritter ,  Richard C. VanAlstine

IPC: H01G7/06

Abstract: A tunable multilayer capacitor is provided. The capacitor comprises a first active electrode in electrical contact with a first active termination and a second active electrode in electrical contact with a second active termination. The capacitor comprises a first DC bias electrode in electrical contact with a first DC bias termination and a second DC bias electrode in electrical contact with a second DC bias termination. A plurality of dielectric layers disposed between the first and second active electrodes and between the first and second bias electrodes. At least a portion of the dielectric layers contain a tunable dielectric material that exhibits a variable dielectric constant upon the application of an applied DC voltage across the first and second DC bias electrodes. A thickness of at least one of the plurality of dielectric layers is greater than about 15 micrometers.

公开(公告)号：US11495406B2

公开(公告)日：2022-11-08

申请号：US16751299

申请日：2020-01-24

Applicant: AVX Corporation

Inventor： Marianne Berolini ,  Jeffrey A. Horn ,  Richard C. VanAlstine

IPC: H01G4/232 ,  H01G4/12 ,  H01G4/30 ,  H01G2/06 ,  H01G4/012 ,  G01R31/01

Abstract: The present invention is directed to a multilayer ceramic capacitor that includes a plurality of active electrodes and at least one shield electrode that are each arranged within a monolithic body and parallel with a longitudinal direction. The capacitor may exhibit a first insertion loss value at a test frequency, which may be greater than about 2 GHz, in a first orientation relative to the mounting surface. The capacitor may exhibit a second insertion loss value at about the test frequency in a second orientation relative to the mounting surface and the capacitor is rotated 90 degrees or more about the longitudinal direction with respect to the first orientation. The longitudinal direction of the capacitor may be parallel with the mounting surface in each of the first and second orientations. The second insertion loss value may differ from the first insertion loss value by at least about 0.3 dB.

公开(公告)号：US11211201B2

公开(公告)日：2021-12-28

申请号：US16751311

申请日：2020-01-24

Applicant: AVX Corporation

Inventor： Marianne Berolini ,  Jeffrey A. Horn ,  Richard C. VanAlstine

IPC: H01G4/012 ,  H01G4/232 ,  H01G4/30

Abstract: The present invention is directed to a multilayer ceramic capacitor. A plurality of active electrodes may be arranged within a monolithic body of the capacitor and parallel with a longitudinal direction. A first shield electrode may be arranged within the monolithic body and parallel with the longitudinal direction. The first shield electrode may be connected with a first external terminal. The first shield electrode may have a first longitudinal edge and a second longitudinal edge that are each aligned with the lateral direction and face away from the first external terminal. The second longitudinal edge may be offset in the longitudinal direction from the first longitudinal edge by a shield electrode offset distance. A second shield electrode may be connected with a second external terminal. The second shield electrode may be approximately aligned with the first shield electrode in the Z-direction.

公开(公告)号：US10943741B2

公开(公告)日：2021-03-09

申请号：US16132537

申请日：2018-09-17

Applicant: AVX Corporation

Inventor： Craig W. Nies ,  Andrew P. Ritter ,  Richard C. VanAlstine

IPC: H01G7/06 ,  H01G4/12 ,  H01G4/30 ,  H01G4/012

Abstract: A tunable multilayer capacitor array is provided. The tunable multilayer capacitor includes a plurality of tunable multilayer capacitors that are connected in parallel. The tunable multilayer capacitor has an initial capacitance value greater than about 0.1 microFarads at an operating voltage greater than about 10 volts. The tunable multilayer capacitor is configured to have a tunable capacitance by applying a DC bias voltage to the tunable multilayer capacitor array.