公开(公告)号：US06795878B2

公开(公告)日：2004-09-21

申请号：US09734115

申请日：2000-12-11

申请人： Aaron Ches Brown ,  Steven Robert Farago ,  Robert James Ramirez ,  Kenneth Lee Wright

发明人： Aaron Ches Brown ,  Steven Robert Farago ,  Robert James Ramirez ,  Kenneth Lee Wright

IPC分类号： G06F1337

CPC分类号： G06F12/0815

摘要： A method, computer program product and data processing system for verifying cumulative ordering. In one embodiment of the present invention a method comprises the step of selecting a memory barrier instruction issued by a particular processor. The method further comprises selecting a first cache line out of a plurality of cache lines to be paired with one or more of the remaining of the plurality of cache lines. If a load memory instruction executed after the memory barrier instruction in the first cache line was identified, then the first cache line selected will be paired with a second cache line. If a load memory instruction executed before the memory barrier instruction in the second cache line was identified, then a pair of load memory instructions has been identified. Upon identifying the second load memory instruction, a first and second reload of the first and second cache lines are identified. Upon identifying the first and second reloads of the first and second cache lines, a determination may be made as to whether the first reload occurred after the second. If the first reload did not occur after the second reload, then a determination may be made as to whether the ownership transaction referencing the first cache line was initiated between the first and second reload. If the ownership transaction was initiated between the first and second reload, then a potential violation of cumulative ordering has been identified.

摘要翻译： 一种用于验证累积排序的方法，计算机程序产品和数据处理系统。 在本发明的一个实施例中，一种方法包括选择由特定处理器发出的存储器屏障指令的步骤。 该方法还包括从多个高速缓存线中选择要与多条高速缓存行中剩余的一条或多条高速缓存行配对的第一高速缓存行。 如果在第一高速缓存行中的存储器障碍指令之后执行的加载存储器指令被识别，则所选择的第一高速缓存行将与第二高速缓存行配对。 如果在第二高速缓存行中的存储器障碍指令之前执行的加载存储器指令被识别，则已经识别出一对加载存储器指令。 在识别第二加载存储器指令时，识别第一和第二高速缓存行的第一和第二重新加载。 在识别第一和第二高速缓存行的第一和第二重新载入时，可以确定在第二高速缓存行之后是否发生第一重新加载。 如果在第二次重新加载之后没有发生第一次重新加载，则可以确定引用第一高速缓存行的所有权交易是否在第一和第二重新加载之间启动。 如果所有权交易在第一次和第二次重新加载之间启动，则已经识别出潜在的累积排序违规。

公开(公告)号：US06934825B1

公开(公告)日：2005-08-23

申请号：US09671513

申请日：2000-09-21

申请人： Steven Robert Farago ,  Robert James Ramirez ,  Kenneth Lee Wright

发明人： Steven Robert Farago ,  Robert James Ramirez ,  Kenneth Lee Wright

IPC分类号： G06F9/34 ,  G06F12/00 ,  G06F12/02

CPC分类号： G06F12/023 ,  Y10S707/99942

摘要： A method, system, and apparatus for placing and removing data elements into a bi-directionally growing first in last out data structure is provided. In one embodiment, in response to a request to place a data element into the data structure, a head pointer is advanced one memory location in a direction indicated by a state of a direction flag. The new data element is placed into the memory location indicated by the head pointer. The position of the head pointer and the base pointer are swapped in preparation for receiving a new data element and the state of the direction flag is reversed to indicate growth of the data structure in the opposite direction. In response to a request to remove a data element from the data structure, the head and base pointers are swapped and the state of the direction flag is reversed. The element indicated by the location pointed to by the head pointer is removed and the head pointer retreats one memory location position in a direction opposite the direction indicated by the direction flag.

摘要翻译： 提供了一种用于将数据元素放置和移除到双向增长的先进数据结构中的方法，系统和装置。 在一个实施例中，响应于将数据元素放入数据结构的请求，头指针在由方向标志的状态指示的方向上前进一个存储器位置。 新数据元素被放置在由头指针指示的存储器位置中。 交换头指针和基指针的位置以准备接收新数据元素，并且方向标志的状态被反转以指示数据结构在相反方向上的增长。 响应于从数据结构中移除数据元素的请求，头和基指针被交换，并且方向标志的状态被反转。 由头指针指向的位置指示的元件被移除，并且头指针在与方向标志指示的方向相反的方向上退回一个存储器位置位置。

公开(公告)号：US06473772B1

公开(公告)日：2002-10-29

申请号：US09213913

申请日：1998-12-17

申请人： Archie Don Barrett, Jr. ,  Jason Raymond Baumgartner ,  Sriram Srinivasan Mandyam ,  Robert James Ramirez ,  Brett Adam St. Onge ,  Kenneth Lee Wright

发明人： Archie Don Barrett, Jr. ,  Jason Raymond Baumgartner ,  Sriram Srinivasan Mandyam ,  Robert James Ramirez ,  Brett Adam St. Onge ,  Kenneth Lee Wright

IPC分类号： G06F1730

CPC分类号： G06F11/261 ,  G06F17/5022 ,  Y10S707/99945 ,  Y10S707/99948

摘要： A method and apparatus for dynamically driving events in a simulation of a data processing system are implemented. Events, or system states, are generated by drivers located at predetermined locations within the simulation model under test. These events, which are drawn from a predetermined class of events, termed “effects,” are driven in response to other events observed by monitors disposed within the simulation model in accordance with a predetermined set of “causes,” and a set of “rules” that map causes to effects. The driving of events is mediated by a library process that receives observed events from the monitors, in the form of data structures, stored them in a database, and passes the effects to be driven to the appropriate driver in accordance with the set of rules, also data structures stored in the database, when a cause corresponds to a observed event.

摘要翻译： 实现了在数据处理系统的仿真中动态地驱动事件的方法和装置。 事件或系统状态由位于被测仿真模型中的预定位置的驱动器产生。这些事件是从预定的事件类别（被称为“效应”）中抽出的，这些事件响应于所设置的监视器观察到的其他事件而被驱动 在模拟模型中根据预定的一组“原因”，以及一组映射导致效果的“规则”。 事件的驱动是通过库过程进行的，该过程从数据结构的形式接收来自监视器的观察事件，将它们存储在数据库中，并根据该组规则将要驱动的效果传递给适当的驱动程序， 还存储在数据库中的数据结构，当原因对应于观察到的事件时。

公开(公告)号：US6021261A

公开(公告)日：2000-02-01

申请号：US760497

申请日：1996-12-05

申请人： Archie Don Barrett, Jr. ,  Sriram Srinivasan Mandyam ,  Brian Walter O'Krafka ,  Brett Adam St. Onge ,  Robert James Ramirez

发明人： Archie Don Barrett, Jr. ,  Sriram Srinivasan Mandyam ,  Brian Walter O'Krafka ,  Brett Adam St. Onge ,  Robert James Ramirez

IPC分类号： G06F11/16 ,  G06F11/267 ,  G06F11/27 ,  G06F11/34 ,  G06F11/00

CPC分类号： G06F11/2242 ,  G06F11/2236 ,  G06F11/3495 ,  G06F11/1641

摘要： A multiprocessor data processing system includes a shared main memory and a plurality of processors connected to the memory utilizing a system bus. Data is transferred utilizing the system bus. The plurality of processors include a first processor and a second processor. The first processor includes a first cache, and the second processor includes a second cache. The multiprocessor data processing system executes a test program. During execution of the test program, a first and a second trace are generated. The first trace is generated by monitoring all events occurring at a first location within the system. The second trace is generated by monitoring all events occurring at a second location within the system. Each event is associated with a time of occurrence of that event. The first trace includes each event which was monitored at the first location and the time associated with each event. The second trace includes each event which was monitored at the second location and the time associated with each event. The first and second traces are stored and utilized to determine if the multiprocessor data processing system is operating correctly.

摘要翻译： 多处理器数据处理系统包括共享主存储器和利用系统总线连接到存储器的多个处理器。 使用系统总线传输数据。 多个处理器包括第一处理器和第二处理器。 第一处理器包括第一高速缓存，第二处理器包括第二高速缓存。 多处理器数据处理系统执行测试程序。 在执行测试程序期间，产生第一和第二迹线。 通过监视系统内第一个位置发生的所有事件来生成第一个跟踪。 通过监视系统内第二个位置发生的所有事件来生成第二个跟踪。 每个事件与该事件发生的时间相关联。 第一个跟踪包括在第一个位置监视的每个事件和与每个事件相关联的时间。 第二个跟踪包括在第二个位置监视的每个事件和与每个事件相关联的时间。 存储和利用第一和第二迹线来确定多处理器数据处理系统是否正常工作。

公开(公告)号：US06285974B1

公开(公告)日：2001-09-04

申请号：US09304538

申请日：1999-05-04

申请人： Sriram Mandyam ,  Brian Walter O'Krafka ,  Ramanathan Raghavan ,  Robert James Ramirez ,  Miwako Tokugawa

发明人： Sriram Mandyam ,  Brian Walter O'Krafka ,  Ramanathan Raghavan ,  Robert James Ramirez ,  Miwako Tokugawa

IPC分类号： G06F1750

CPC分类号： G06F9/52

摘要： One aspect of the invention relates to a method for detecting architectural violations in a multiprocessor computer system. In one version of the invention, the method includes the steps of generating a testcase instruction stream having a plurality of instructions, executable by the processors, which access a memory which is shared by the processors; detecting dependent instructions in the testcase instruction stream; and modifying the testcase instruction stream by inserting logging instructions in the testcase in the testcase instruction stream which cause data associated with observable instructions to be written to a logging memory by writing a first sequence of unique monotonically increasing values to the memory. Thereafter, a second sequence of values is read from the memory location and a window of observed values is defined, wherein the window has a highest observable value and a lowest observable value where the highest observable value is set to the highest value of the first sequence and the lowest observable value is set to the lowest value of the first sequence and wherein the lowest observable value is updated with a next observable value from the first sequence whenever the value of an individual read from the second sequence is higher than the lowest observable value so that a determination can be made whether individual values in the second sequence are within the window.

摘要翻译： 本发明的一个方面涉及一种用于检测多处理器计算机系统中的结构违规的方法。 在本发明的一个版本中，该方法包括以下步骤：生成具有可由处理器执行的多个指令的测试用例指令流，该指令访问由处理器共享的存储器; 检测测试用例指令流中的相关指令; 以及通过将测试用例中的测试指令插入到测试用例指令流中来修改测试用例指令流，该指令流通过向存储器写入唯一的单调递增值的第一序列而将与可观察指令相关联的数据写入记录存储器。 此后，从存储器位置读取第二序列值，并且定义观察值的窗口，其中窗口具有最高可观测值和最低可观测值，其中最高可观测值被设置为第一序列的最高值 并且所述最低可观测值被设置为所述第一序列的最低值，并且其中，当从所述第二序列读取的个体的值高于所述最低可观察值时，所述最低可观察值用来自所述第一序列的下一可观测值更新 使得可以确定第二序列中的各个值是否在窗口内。

公开(公告)号：US5928334A

公开(公告)日：1999-07-27

申请号：US827549

申请日：1997-03-28

申请人： Sriram Mandyam ,  Brian Walter O'Krafka ,  Ramanathan Raghavan ,  Robert James Ramirez ,  Miwako Tokugawa

发明人： Sriram Mandyam ,  Brian Walter O'Krafka ,  Ramanathan Raghavan ,  Robert James Ramirez ,  Miwako Tokugawa

IPC分类号： G06F9/46 ,  G06F15/16 ,  G06F12/00

CPC分类号： G06F9/52

摘要： One aspect of the invention relates to a method for detecting synchronization violations in a multiprocessor computer system having a memory location which controls access to a portion of memory shared by the processors, the memory location having at least one lock bit indicating whether the portion of memory is locked by one of the processors and a plurality of bits for storing a data value. The method comprises reading the memory location by an individual processor; testing the lock bit to determine whether the portion of memory is locked; if the portion of memory is not locked; asserting the lock bit to indicate the portion of memory is locked; incrementing the data value to represent a global access count; writing the lock bit and the data value back to the memory location; and incrementing a data value stored in a memory location associated with the individual processor to indicate an individual access count by the individual processor. The individual access counts for each processor are then summed and compared to the global access count to determine whether a synchronization violation has occurred.

摘要翻译： 本发明的一个方面涉及一种用于检测多处理器计算机系统中的同步违规的方法，所述多处理器计算机系统具有控制对由所述处理器共享的存储器的一部分的访问的存储位置，所述存储器位置具有指示所述存储器部分的至少一个锁定位 被处理器之一锁定，并且存储用于存储数据值的多个位。 该方法包括由单个处理器读取存储器位置; 测试锁定位以确定存储器的部分是否被锁定; 如果内存部分没有锁定; 断言锁定位指示存储器的部分被锁定; 增加数据值以表示全局访问计数; 将锁定位和数据值写回内存位置; 并且增加存储在与所述单独处理器相关联的存储器位置中的数据值，以指示所述单独处理器的单独访问计数。 然后将每个处理器的个人访问计数相加并与全局访问计数进行比较，以确定是否发生同步冲突。