公开(公告)号：US11698658B1

公开(公告)日：2023-07-11

申请号：US17833306

申请日：2022-06-06

Applicant: Acacia Communications, Inc.

Inventor： Gavin Allen ,  Ian Dedic ,  Bo Yang ,  Tarun Gupta

IPC: G06F1/10 ,  H03K3/037

CPC classification number: G06F1/10 ,  H03K3/037

Abstract: A method system, and apparatus for adjusting skew in a circuit comprising feeding an input clock into a first push-pull source follower stage, feeding an inverse of an input clock bar into a first CMOS inverter stage, creating an output clock based on an equal contribution of the input clock of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage, feeding the input clock bar into a first push-pull source follower stage, feeding an inverse of the input clock into a first CMOS inverter stage, and creating an output clock based on an equal contribution of the input clock bar of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage.

公开(公告)号：US11543850B1

公开(公告)日：2023-01-03

申请号：US16777968

申请日：2020-01-31

Applicant: Acacia Communications, Inc.

Inventor： Ian Dedic ,  Gavin Allen ,  David Enright ,  Bo Yang ,  Tarun Gupta

IPC: G06F1/08 ,  H03B5/12 ,  H03F3/50

Abstract: An apparatus and system for a clock buffer. The clock buffer comprises a source follower, and the source follower comprises a voltage source and a resistor.

公开(公告)号：US12130656B1

公开(公告)日：2024-10-29

申请号：US18343841

申请日：2023-06-29

Applicant: Acacia Communications, Inc.

Inventor： Gavin Allen ,  Ian Dedic ,  Bo Yang ,  Taran Gupta

IPC: G06F1/10 ,  H03K3/037

CPC classification number: G06F1/10 ,  H03K3/037

Abstract: A method system, and apparatus for adjusting skew in a circuit comprising feeding an input clock into a first push-pull source follower stage, feeding an inverse of an input clock bar into a first CMOS inverter stage, creating an output clock based on an equal contribution of the input clock of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage, feeding the input clock bar into a first push-pull source follower stage, feeding an inverse of the input clock into a first CMOS inverter stage, and creating an output clock based on an equal contribution of the input clock bar of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage.